How to covert AHB BUS monitor VIP to AHB Master Port monitor

 

Below is an example on how to covert the AHB Bus monitor to a Port Monitor for Master:

 

Step 1: in the TBTop, do as below(wire-connection):

 

//****************************************************************

// AHB Monitor interface for Master 1

//****************************************************************

  //for AHB Master Monitor VIP

  wire[3:0]            hmaster_m1_mn;

  wire[1:0]            hbusreq_m1_mn;

  wire[1:0]            hsel_m1_mn;

  wire[1:0]            hgrant_m1_mn;

 

  assign  hmaster_m1_mn = (hmaster==1)? 'h1:'h0;

  assign  hsel_m1_mn = {1'b1,1'b0};                                         

  assign  hgrant_m1_mn = {hgrant_m1,~hgrant_m1};

  assign  hbusreq_m1_mn = {hbusreq_m1,1'b0};

 

   AhbMonitorInterface intf_mon_m1(

        .hclk               ( hclk ),

        .hresetn       ( hresetn ),

        .haddr           ( haddr_m1 ),

        .hburst         ( hburst_m1 ),

        .hmastlock   ( 1'b0  ),

        .hprot           ( 4'b0),

        .hrdata         ( hrdata_m1 ),

        .hready        ( hready_m1 ),

        .hresp           ( hresp_m1 ),

        .hsize            ( hsize_m1 ),

        .htrans          ( htrans_m1 ),

        .hwdata       ( hwdata_m1 ),

        .hwrite         ( hwrite_m1 ),

        .hmaster      ( hmaster_m1_mn ),

        .hsel              ( hsel_m1_mn),

        .hbusreq      ( hbusreq_m1_mn ),

        .hgrant         ( hgrant_m1_mn ),

        .hlock            (6'b0 ),

        .hsplit_s0   (6'b0  ),

        .hsplit_s1   ( 6'b0  ),

        .hsplit_s2   ( 6'b0  ),

        .hsplit_s3   ( 6'b0  ),

        .hsplit_s4   ( 6'b0  ),

        .hsplit_s5   ( 6'b0  ),

        .hsplit_s6   (6'b0   ),

        .hsplit_s7   ( 6'b0  ),

        .hsplit_s8   ( 6'b0  ),

        .hsplit_s9   ( 6'b0  ),

        .hsplit_s10   (6'b0   ),

        .hsplit_s11   (6'b0   ),

        .hsplit_s12   ( 6'b0  ),

        .hsplit_s13   (6'b0   ),

        .hsplit_s14   ( 6'b0  ),

        .hsplit_s15   ( 6'b0  )

 

   );

 

Step 2: in the vmm_env, create a fake port monitor for Master, pass the interface, configuration to this monitor VIP

 

class ahbEnv extends vmm_env ;

 

  virtual AhbMonitorInterface.Monitor AhbMonitorBindM1;

  dw_vip_ahb_monitor_rvm       monitor_vip_m1 ;

  dw_vip_ahb_system_configuration  cfg_sys_mn;

 

  virtual function void gen_cfg ();

      cfg_sys_mn = new(,2,2,);

      cfg_sys_mn.m_enHdataWidth = dw_vip_amba_configuration::HDATA_WIDTH_32;

      cfg_sys_mn.m_enHaddrWidth = dw_vip_amba_configuration::HADDR_WIDTH_32;

  endfunction

 

  virtual function void build ();

    begin

      super.build();

      //Master port monitor side

      monitor_activity_ch_m1 = new("Monitor Activity Channel","MAct1");

      monitor_vip_m1 = new("AHB MONITOR",AhbMonitorBindM1,cfg_sys_mn,monitor_activity_ch_m1);

endfunction

 

 

  virtual task start ();

    begin

        super.start();

       monitor_vip_m1.start_xactor();

 end

endtask

 

endclass

 

Step3: in the Scoreboard, get object from the port monitor channel:

 

class ahbSB extends vmm_xactor;

 

  task ahbSB::main();

    super.main();

 

    fork

 

      while (1) begin // from M1 montor

                  wait_if_stopped_or_empty(monitor_chan_m1);

                  monitor_chan_m1.get(monitor_trans_m1);

                  monitor_trans_m1.m_nSrcMaster=1;

                  $cast(cpy_m1,monitor_trans_m1.copy());

                  quick_compare(cpy_m1);

                  num_of_trans++;

                  if(num_of_trans==total_num_of_trans) this.notify.indicate(this.DONE);

      end