verilog 写的1602动态计数器（完善过）

来源：互联网发布：python游戏服务器开发编辑：程序博客网时间：2024/04/30 13:07

由于前面一个帖子的代码有点瑕疵，这个完善了一点，我吧第二行的第一个作为个位数，第一行的第一位作为十位数，按照01--99进行计数。哈哈，动态刷新哦！！网上太难找到这样的例子了！本人刚学会就贡献给大家，作为初学。请抛砖

module LCD
(
  rst,
  key1,
  clk,
  rw,
  rs,
  en,
  data,
);
input clk,rst,key1;
output rs,en,rw;
output [7:0] data;

reg rs,en_sel;
reg [7:0] data;
reg [15:0] add;
reg [15:0]count,count1,jishu,cnt;  //LCD CLK 分频计数器
reg lcd_clk;

reg [7:0] next,xianshi,two;
parameter state0 =6'h00,     //设置8位格式,2行,5*7   8'h38;
    state1 =6'h01,  //整体显示,关光标,不闪烁 8'h0C    闪烁 8'h0e
    state2 =6'h02,  //设定输入方式,增量不移位 8'h06
    state3 =6'h03,  //清除显示     8'h01
    state4 =6'h04,  //显示第一行的指令  80H
    state5 =6'h05,  //显示第二行的指令  80H+40H

    scan =6'h06,
    nul  =6'h07;

parameter data0 =6'h10,
    data1 =6'h11;

always @(posedge clk )   //获得LCD时钟
begin
  count<=count+1;
  if(count==25000)
  begin
   count<=0;
   lcd_clk<=~lcd_clk;
  end
end

initial begin xianshi<=8'b00110001;two<=8'b00110000; en_sel<=1; end

always @(posedge lcd_clk or negedge rst )
begin
  if(!rst)
  begin
   next<=state0;
   xianshi<=8'b00110001;
   two<=8'b00110000;
  end
  else
  begin
   case(next)
    state0 :
     begin rs<=0; data<=8'h38; next<=state1; end
    state1 :
     begin rs<=0; data<=8'h0e; next<=state2; end
    state2 :
     begin rs<=0; data<=8'h06; next<=state3; end
    state3 :
     begin rs<=0; data<=8'h01; next<=state4; end

    state4 :
     begin rs<=0; data<=8'h80; next<=data0; end
    data0 :
     begin rs<=1; data<=two; next<=state5 ; end

    state5:
     begin rs<=0;data<=8'hC0; next<=data1; end //显示第二行
    data1 :
     begin rs<=1; data<=xianshi; next<=scan ; end

    scan :
    begin
     if(add==500)
     begin
       en_sel<=1;
       add<=0;
       xianshi<=xianshi+8'b00000001;
       if(xianshi==8'b00111001)
       begin
        xianshi<=8'b00110001;
        two<=two+8'b00000001;
        if(two==8'b00111001)
        begin
         two<=8'b00110001;
        end
       end
       next<=state0;

     end
     else
     begin
      add<=add+1;
      en_sel<=0;
      next<=data0;
     end
    end

    default:   next<=state0;
   endcase
  end
end
assign en=lcd_clk && en_sel;
assign rw=0;
endmodule