p1010 nand_uboot
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1. Build the NAND Boot binary using P1010RDB_NAND_config option on u-boot,
a. Configure u-boot to build NAND boot binary for platform,
i. make ARCH=powerpc CROSS_COMPILE=/opt/freescale/usr/local/gcc-4.5.55-eglibc-2.11.55/powerpc-linux-gnu/bin/powerpc-linux-gnu- *_NAND_config
b. Build the binary,
i. make ARCH=powerpc CROSS_COMPILE=/opt/freescale/usr/local/gcc-4.5.55-eglibc-2.11.55/powerpc-linux-gnu/bin/powerpc-linux-gnu-
ii. This will build u-boot-nand.bin
2. Flash the NAND boot binary on NAND Flash.
a. For this we can use Code Warrior IDE 10.1 or else the any other bootloader which has NAND Flash driver can be used. For more information on Code warrior based method, please refer to platform BSP user manual.
Using other boot method to flash NAND boot binary, steps are given below.
=> tftp 1000000 u-boot-nand.bin
=> nand erase 0 100000
=> nand write 1000000 0 100000
3. Change the Switch settings for NAND boot.
Test Log:
Boot from SPIe Flash
U-Boot 2010.12-00185-ga3ee01e (Mar 22 2011 - 09:16:18)
CPU: P1010E, Version: 1.0, (0x80f90010)
Core: E500, Version: 5.1, (0x80212151)
Clock Configuration:
CPU0:800 MHz,
CCB:400 MHz,
DDR:400 MHz (800 MT/s data rate) (Asynchronous), L1: D-cache 32 kB enabled
I-cache 32 kB enabled
Board: P1010RDB
I2C: ready
SPI: ready
DRAM: 1 GiB (DDR3, 32-bit, CL=6, ECC off)
L2: 256 KB enabled
NAND: NAND_ECC_NONE selected by board driver. This is not recommended !!
32 MiB
SF: Detected S25FL128P_64K with page size 256, total 16 MiB
EEPROM: Invalid ID (87 87 87 87)
PCIe1: Root Complex of mini PCIe Slot, no link, regs @ 0xffe0a000
PCIe1: Bus 00 - 00
PCIe2: Endpoint of PCIe Slot, no link, regs @ 0xffe09000
PCIe2: Bus 01 - 01
In: serial
Out: serial
Err: serial
Net: eTSEC1, eTSEC2, eTSEC3
Hit any key to stop autoboot: 0
=>
=> nand erase.chip
NAND erase.chip: device 0 whole chip
Bad block table found at page 65504, version 0x01
Bad block table found at page 65472, version 0x01
Skipping bad block at 0x01ff0000
Skipping bad block at 0x01ff4000
Skipping bad block at 0x01ff8000
Skipping bad block at 0x01ffc000
OK
=> tftp 1000000 u-boot-nand.bin
TFTP from server 192.168.1.10; our IP address is 192.168.1.2
Filename 'u-boot-nand.bin'.
Load address: 0x1000000
Loading: #################################################################
#######
done
Bytes transferred = 364232 (58ec8 hex)
=> nand write 1000000 0 100000
NAND write: device 0 offset 0x0, size 0x100000
1048576 bytes written: OK
Change switch settings for NAND Boot
On P1010RDB switch settings for NAND boot are,
SW1.1-SW1.8 = 00001010
SW2.1-SW2.8 = 11011000
SW3.1-SW3.4 = 0111
SW4.1-SW4.4 = 1000
SW6.1-SW6.4 = 1001
Note: Make sure that J11 and J12 Jumpers are mounted on board to disable ECC checking while boot.
· configuration for PCI
Kernel Configure Tree View Options
Description
Bus options --->
[*] PCI support
Enable PCI host bridge
Device Drivers --->
Network device support --->
[*] Ethernet (10 or 100Mbit) --->
[*] EISA, VLB, PCI and on board controllers
<*> Intel(R) PRO/100+ support
PCI Intel(R) PRO/100 support
Device Drivers --->
Network device support --->
[*] Ethernet (1000Mbit) --->
<*> Intel (R) PRO/1000 Gigabit Ethernet support
PCI Intel Pro/1000 support and
· configuration for PCIe with MSI interrupts. (If using intx interrupts just deselect the Mesage Signaled Interrupts option)
Kernel Configure Tree View Options
Description
Bus options --->
[*] PCI Express support
[*] Root Port Advanced Error Reporting support
[*] Message Signaled Interrupts (MSI and MSI-X)
[*] Enable deprecated pci_find_* API
Enable PCIe support Enable MSI suppport
Device Drivers --->
Network device support --->
[*] Ethernet (1000Mbit) --->
<*> Intel (R) PRO/1000 PCI-Express Gigabit Ethernet support
PCIe Intel Pro/1000 support and
Compile-time Configuration Options
· configuration for PCI
Option
Values
Default Value
Description
CONFIG_PCI
y/n
y
Enable PCI host bridge
CONFIG_PCI_DOMAINS
y/n
y
Enable PCI domains
CONFIG_NET_PCI
y/n
y
Enable network PCI
CONFIG_E100
y/m/n
y
Enable Intel Pro/100+ driver
CONFIG_E1000
y/m/n
y
Enable Intel Pro/1000 driver
· configuration for PCIe
Option
Values
Default Value
Description
CONFIG_PCIEPORTBUS
y/n
y
Enable PCIe general support
CONFIG_PCI_MSI
y/n
y
Enable MSI support
CONFIG_E1000E
y/m/n
m
Intel(R) PRO/1000 PCI Express Gigabit Ethernet support
Source Files
The driver source is maintained in the Linux kernel source tree.
Source File
Description
arch/powerpc/sysdev/fsl_pci.c
The e500 platform PCI/PCIe host bridge support source
drivers/net/e100.c
Intel Pro/100+ driver source code
drivers/net/e1000/
Intel Pro/1000 driver source code
/linux/drivers/net/e1000e/
Intel Pro/1000 PCI Express Gigabit Ethernet Card driver source code
U-boot Configuration
Execute the following command at the u-boot prompt
setenv hwconfig "fsl_p1010mux:tdm_can=can"
save
Platform support --->
[*] Freescale Book-E Machine Type --->
[*] Freescale FlexCAN
[*] Networking support -->
<*> CAN bus subsystem support --->
--- CAN bus subsystem support
<*> Raw CAN Protocol (raw access with CAN-ID filtering)
<*> Broadcast Manager CAN Protocol (with content filtering)
CAN Device Drivers --->
< > Virtual Local CAN Interface (vcan)
<*> Platform CAN drivers with Netlink support
[*] CAN bit-timing calculation
<> Microchip MCP251x SPI CAN controllers
*** Flexcan Platform Selection ***
FlexcanPlatform selection (OpenFirmwareType Flexcan support)--->
<*> Support fro FLEXCAN drivers
< > Support for Freescale MSCAN based chips
< > Philips/NXP SJA1000 devices --->
CAN USB interfaces --->
[ ] CAN devices debugging messages
[root@P1020RDB flexcan]# cat /proc/interrupts
CPU0
17: 0 OpenPIC Level phy_interrupt, phy_interrupt
20: 0 OpenPIC Level fsldma-chan
21: 0 OpenPIC Level fsldma-chan
22: 0 OpenPIC Level fsldma-chan
23: 0 OpenPIC Level fsldma-chan
29: 513 OpenPIC Level eth0_g0_tx
48: 4 OpenPIC Level can0
59: 2 OpenPIC Level fsl-espi
61: 4 OpenPIC Level can1
72: 0 OpenPIC Level mmc0
74: 6 OpenPIC Level fsl-sata
LOC: 24069 Local timer interrupts
# ip link set can0 up type can bitrate 125000
cantest can0 12345678#123412341234
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