ARM1176JZF-S/S3C6410 内存地…

这是一份对于ARM1176JZF-S芯片上MMU内存地址转换/映射过程的整理，内容完全来自ARM官网的技术手册。

ARM1176JZF-S属于ARMv6产品系列，支持两种页表项的格式，一种是向ARMv4和ARMv5兼容的格式，另一新是ARMv6的新格式。v4/v5的格式在相应的技术手册里描述得非常清楚，但是对于v6格式的描述显得有点散，所以本文只关注ARMv6格式。

内容保持英文原文，没有翻译以免造成误解弄巧成拙。

Level 1 Translation

When the CP15 Control Register c1 Bit 23 is set to 1 in thecorresponding world, the subpage AP bits are disabled and the pagetables have support for ARMv6 MMU features.

LEVEL 1 DESCRIPTOR FORMAT

As shown in Figure above, bits [1:0] of a level 1 page table entrydetermine the type of the entry.

Explanation of each bit:

BitsMeaningBits [1:0] == b00Translation fault.Bits [1:0] == b01The entry points to a second-level page table, called a Coarse pagetable. Figure 6.8 shows the formats of the possible entries in theCoarse page table.Bits [1:0] == b10The entry points to a either a 1MB Section of memory or a 16MBSupersection of memory. Bit [18] of the descriptor selects betweena Section and a Supersection. For details of supersections seeSupersections.Bits [1:0] == b11Reserved.SBZSBZ = Should Be Zero, there bits should be set as 0 value.NSDefines the world for the processor:0 = Secure, reset value,1 =Non-secure.DomainA domain is a collection of memory regions. ARM1176JZF-S supports16 Domains in the Secure world and 16 Domains in the Non-secureworld. Domains provide support for multi-user operating systems.All regions of memory have an associated domain.nGThe Not-Global (nG) bit, determines if the translation is marked asglobal (0), or process-specific (1) in the TLB. Forprocess-specific translations the translation is inserted into theTLB using the current ASID, from the ContextID Register, CP15c13.SThe Shared (S) bit, determines if the translation is for Non-Shared(0), or Shared (1) memory. This only applies to Normal memoryregions. Device memory can be Shared or Non-Shared as determined bythe TEX bits and the C and B bits.XNThe Execute-Never (XN) bit, determines if the region is Executable(0) or Not-executable (1).APXThree access permission bits.The access permissions extension (APX)bit, provides an extra access permission bit.See “AccessPermissions”.APPARM1176JZF-S processors do not support the P bit.TEXSee “TEX, C and B bits”.CB

TEX, C AND B BITS

TEX, C AND B BITS PROVIDE OPTIONS FOR INNER AND OUTERCACHABILITY.

The ARMv6 MMU architecture originally defined five bits to describeall of the options for inner and outer cachability. These fivebits, the Type Extension Field, TEX[2:0], Cacheable, C, andBufferable, B bits, are set in the descriptors.

Few applications make use of all these options simultaneously. Forthis reason, a new configuration bit, TEX remap, bit [28] in theCP15 Control Register, permits the core to support a smaller numberof options by using only the TEX[0], C and B bits.

The OS can configure this subset of options through a remapmechanism for these TEX[0], C, and B bits. The TEX[2:1] bits in thedescriptor then become 2 OS managed page table bits.

See detail of ARM1176JZF-S Technical Reference Manual 6.6.1 forTexRemap=0 configuration/TexRemap=1 configuration.

ACCESS PERMISSIONS

The access permission bits control access to the correspondingmemory region. If an access is made to an area of memory withoutthe required permissions, then a permission fault is raised.

The access permissions are determined by a combination of the APand APX bits in the page table, and the S and R bits in CP15Control Register c1. For page tables not supporting the APX bit,the value 0 is used.

Access permission bit encoding:

VIRTUAL-PHISICAL ADDRESS TRANSLATION

Translation for a 1MB section, ARMv6 format

Level 2 Translation

LEVEL 2 DESCRIPTOR FORMAT

Explanation of each bit:

BitsMeaningBits [1:0] == b00Translation fault.Bits [1:0] == b01The entry points to a 64KB Large page in memory.Bits [1:0] == b1xThe entry points to a 4KB Extended small page in memory.Bit [0] ofthe entry is the XN bit for the entry.

 

VIRTUAL-PHISICAL ADDRESS TRANSLATION

Large page table walk, ARMv6 format:

4KB extended small page translations, ARMv6 format: