Samsung ATM920T S3C2410x Initialization Code- -

http://www.51usb.com/

注：

1)  CPU:   Samsung S3C2410x

    SDRAM: 64MB/Bank6

    Flash: 16MB/NAND or 16MB/Intel Strata NOR(bank0)

2)  写一个空的C_Entry()函数，然后在ADS1.2中编译后生成bin文件直接烧入Flash即可作为一个简单的初始化代码，完成s3c2410的初始化，后续调试代码可以直接下载到SDRAM中.(RAM_STARTADDRESS=0x30000000)

;=====================================
; NAME: 2410INIT.S ;
; DESC: S3C2410 EVB Startup Code ;
; AUTH: [e-mail] ;
; REV: 1.0.1 ;
; DATE: MAY,2003 ;
;=====================================

GBLL IDE_TYPE
GBLL CPU_CLK_200
IDE_TYPE SETL {TRUE}     ;TRUE=ADS1.2
                         ;FALSE=SDT2.5
[ IDE_TYPE
    GET option.s
    GET memcfg.s
    GET 2410addr.s ;here GET means INCLUDE used in C language
|
    GET option.a
    GET memcfg.a
    GET 2410addr.a
]

;Pre-defined constants
USERMODE EQU 0x10
FIQMODE EQU 0x11
IRQMODE EQU 0x12
SVCMODE EQU 0x13
ABORTMODE EQU 0x17
UNDEFMODE EQU 0x1b
MODEMASK EQU 0x1f ;This means System Mode.
NOINT EQU 0xc0 ;

;The location of stacks

FIQStack EQU _STACK_BASEADDRESS
IRQStack EQU FIQStack+0x1000
AbortStack EQU IRQStack+0x1000
UndefStack EQU AbortStack+0x400
SVCStack EQU UndefStack+0x400
UserStack EQU SVCStack+0x1000
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
MACRO
    $HandlerLabel HANDLER $HandleLabel
    ; HANDLER is macroname
    ; $HandlerLabel is special macro name
    ; $HandleLabel is a variable
$HandlerLabel
    sub sp,sp,#4 ;decrement sp(to store jump address); sp<----sp - 4, ARM Stack is Full_Decending
    stmfd sp!,{r0} ;PUSH the work register to stack(lr does not push because it return to original address)
    ldr r0,=$HandleLabel ;load the address of HandleXXX to r0
    ldr r0,[r0] ;load the contents(service routine start address) of HandleXX
    str r0,[sp,#4] ;store the contents(ISR) of HandleXXX to stack
    ldmfd sp!,{r0,pc} ;POP the work register and pc(jump to ISR)
MEND
;===============================================================

IMPORT |Image$$RO$$Limit| ; End of ROM code (=start of ROM data)
IMPORT |Image$$RW$$Base| ; Base of RAM to initialise
IMPORT |Image$$ZI$$Base| ; Base and limit of area
IMPORT |Image$$ZI$$Limit| ; to zero initialise

AREA Init,CODE,READONLY
    CODE32
    ENTRY

b ResetHandler ;
b HandlerUndef ;handler for Undefined mode 0x4
b HandlerSWI ;handler for SWI interrupt 0x8
b HandlerPabort ;handler for PAbort 0xC
b HandlerDabort ;handler for DAbort 0x10
b . ;reserved 0x14
b HandlerIRQ ;handler for IRQ interrupt 0x18
b HandlerFIQ ;handler for FIQ interrupt 0x1C




HandlerFIQ HANDLER HandleFIQ
HandlerIRQ HANDLER HandleIRQ
HandlerUndef HANDLER HandleUndef
HandlerSWI HANDLER HandleSWI
HandlerDabort HANDLER HandleDabort
HandlerPabort HANDLER HandlePabort
;=======
; ENTRY
;=======
ResetHandler

;Initialize stacks
bl InitStacks
;=============================
; Configure Crucial Peripherals
;=============================
ldr r0,=WTCON ;watch dog disable @0x5300_0000
ldr r1,=0x0 ;= means 0x0 is 32bit contant
str r1,[r0] ;

ldr r0,=INTMSK ;
ldr r1,=0xffffffff ;all interrupt disable
str r1,[r0]

ldr r0,=INTSUBMSK
ldr r1,=0x7ff ;
str r1,[r0]

;To reduce PLL lock time, adjust the LOCKTIME register.
ldr r0,=LOCKTIME
ldr r1,=0xffffff
str r1,[r0]

;Configure MPLL
ldr r0,=MPLLCON
ldr r1,=((M_MDIV<<12)+(M_PDIV<<4)+M_SDIV) ;Fin=12MHz,Fout=100MHz
str r1,[r0]
;=============================
; Configure MEMORY CONTROLLER
;=============================
;Set memory control registers according to SMRDATA section
ldr r0,=SMRDATA
ldr r1,=BWSCON ;BWSCON Address
add r2, r0, #52 ;End address of SMRDATA
0
    ldr r3, [r0], #4 ; load r3 from r0, then r0=r0+4
    str r3, [r1], #4 ; store r3 to r1, then r1=r1+4
    cmp r2, r0
    bne %B0
;=============================
; Clear SDRAM
;=============================
ldr r0,=GPFCON
ldr r1,=0x55aa ;GPF[7:4]--output GPF[3:0]--EINT[3:0]
str r1,[r0]
ldr r0,=GPFUP
ldr r1,=0xff ;GPF up-pull resistors are disabled
str r1,[r0]
ldr r0,=GPFDAT
ldr r1,=0x0
str r1,[r0] ;

mov r1,#0
mov r2,#0
mov r3,#0
mov r4,#0
mov r5,#0
mov r6,#0
mov r7,#0
mov r8,#0

ldr r9,=0x3ff0000 ;Lower 32MB
ldr r0,=0x30010000 ;leave 64kb for code//=0x30000000
LOOP ;SDRAM clear
stmia r0!,{r1-r8} ;stack starts from 0x30000000,
subs r9,r9,#32 ;
bne LOOP
;=============================
; Exception Vector Table Setup
;=============================
EXCEPTION_VECTOR_TABLE_SETUP
LDR r0, =HandleReset ; Exception Vector Table Memory Loc.
LDR r1, =ExceptionHandlerTable ; Exception Handler Assign
MOV r2, #8 ; Number of Exception is 8
ExceptLoop
LDR r3, [r1], #4
STR r3, [r0], #4
SUBS r2, r2, #1
BNE ExceptLoop
;====================================================
;Copy and paste RW data/zero initialized data
;====================================================
ldr r0, =|Image$$RO$$Limit| ; Get pointer to ROM data
ldr r1, =|Image$$RW$$Base| ; and RAM copy
ldr r3, =|Image$$ZI$$Base| ; Zero init base => top of initialised data
cmp r0, r1 ; Check that they are different
beq %F2 ; F means forward
1

    cmp r1, r3 ; Copy init data
    ldrcc r2, [r0], #4 ;--> LDRCC r2, [r0] + ADD r0, r0, #4
    strcc r2, [r1], #4 ;--> STRCC r2, [r1] + ADD r1, r1, #4
    bcc %B1 ;B means backward
2

    ldr r1, =|Image$$ZI$$Limit| ; Top of zero init segment
    mov r2, #0
3

    cmp r3, r1 ; Zero init
    strcc r2, [r3], #4
    bcc %B3
;====================================================
; Now change to user mode and set up user mode stack.
;====================================================
MRS r0, cpsr
BIC r0, r0, #MODEMASK ;MODEMASK=0X1F
ORR r0, r0, #USERMODE|NOINT ;R
MSR cpsr_cxsf, r0
LDR sp, =UserStack
;====================================================
;Jump To C Routines
;====================================================
IMPORT C_Entry
bl C_Entry ;Don not use main() because ......
;bl .
;====================================================
;Initialize Stacks
;====================================================
;function initializing stacks
InitStacks
;Don not use DRAM,such as stmfd,ldmfd......
;SVCstack is initialized before
;Under toolkit ver 2.5, 'msr cpsr,r1' can be used instead of 'msr cpsr_cxsf,r1'
mrs r0,cpsr
bic r0,r0,#MODEMASK ;MODEMASK=0x1f
orr r1,r0,#UNDEFMODE|NOINT ;r1=0xDB
msr cpsr_cxsf,r1 ;UndefMode
ldr sp,=UndefStack

orr r1,r0,#ABORTMODE|NOINT
msr cpsr_cxsf,r1 ;AbortMode
ldr sp,=AbortStack

orr r1,r0,#IRQMODE|NOINT
msr cpsr_cxsf,r1 ;IRQMode
ldr sp,=IRQStack

orr r1,r0,#FIQMODE|NOINT
msr cpsr_cxsf,r1 ;FIQMode
ldr sp,=FIQStack

bic r0,r0,#MODEMASK|NOINT
orr r1,r0,#SVCMODE
msr cpsr_cxsf,r1 ;SVCMode
ldr sp,=SVCStack

;USER mode has not be initialized.

mov pc,lr ;´Ó¶ÑÕ»³õʼ»¯³ÌÐòÖзµ»Ø
;The LR register won not be valid if the current mode is not SVC mode.
;====================================================
;The following DATA section is used to init MEMORY CONTROLLER
;====================================================
LTORG
SMRDATA DATA
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;in ADS1.2 help documents, there is the following discription about DATA directive:
;;;;The DATA directive is no longer needed. It is ignored by the assembler.;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Memory configuration should be optimized for best performance
; The following parameter is not optimized.
; Memory access cycle parameter strategy
; 1) The memory settings is safe parameters even at HCLK=75Mhz.
; 2) SDRAM refresh period is for HCLK=75Mhz.

DCD (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
;DCD ((B6_BWSCON<<24)+(B7_BWSCON<<28))
DCD ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) ;GCS0
DCD ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) ;GCS1
DCD ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) ;GCS2
DCD ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) ;GCS3
DCD ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) ;GCS4
DCD ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) ;GCS5
DCD ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) ;GCS6
DCD ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) ;GCS7
DCD ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+REFCNT)
DCD (0x31|0x80) ;SCLK power saving mode, BANKSIZE 64M/64M, 4-burst
DCD 0x30 ;MRSR6 CL=3clk
DCD 0x20 ;MRSR7
;===========================================
; Exception Vector Function Definition
; Consist of function Call from C-Program.
;===========================================
SystemResetHandler
b ResetHandler
SystemUndefinedHandler
IMPORT ISR_UndefHandler
STMFD sp!, {r0-r12,lr}
B ISR_UndefHandler
LDMFD sp!, {r0-r12, pc}^

SystemSwiHandler
STMFD sp!, {r0-r12,lr}
LDR r0, [lr, #-4]
BIC r0, r0, #0xff000000
CMP r0, #0xff
BEQ MakeSVC
LDMFD sp!, {r0-r12, pc}^
MakeSVC
MRS r1, spsr
BIC r1, r1, #MODEMASK
ORR r2, r1, #SVCMODE
MSR spsr_cf, r2
LDMFD sp!, {r0-r12, pc}^

SystemPrefetchHandler
IMPORT ISR_PrefetchHandler
STMFD sp!, {r0-r12, lr}
B ISR_PrefetchHandler
LDMFD sp!, {r0-r12, lr}
SUBS pc, lr, #4

SystemAbortHandler
IMPORT ISR_AbortHandler
STMFD sp!, {r0-r12, lr}
B ISR_AbortHandler
LDMFD sp!, {r0-r12, lr}
SUBS pc, lr, #8

SystemReserv
SUBS pc, lr, #4

SystemIrqHandler
IMPORT ISR_IrqHandler
STMFD sp!, {r0-r12, lr}
BL ISR_IrqHandler
LDMFD sp!, {r0-r12, lr}
SUBS pc, lr, #4

SystemFiqHandler
IMPORT ISR_FiqHandler
STMFD sp!, {r0-r7, lr}
BL ISR_FiqHandler
LDMFD sp!, {r0-r7, lr}
SUBS pc, lr, #4

ALIGN
AREA RomData, DATA, READONLY
ExceptionHandlerTable
DCD SystemResetHandler
DCD SystemUndefinedHandler
DCD SystemSwiHandler
DCD SystemPrefetchHandler
DCD SystemAbortHandler
DCD SystemReserv
DCD SystemIrqHandler
DCD SystemFiqHandler

AREA RamData, DATA, READWRITE
^ _ISR_STARTADDRESS
HandleReset # 4
HandleUndef # 4
HandleSWI # 4
HandlePabort # 4
HandleDabort # 4
HandleReserved # 4
HandleIRQ # 4
HandleFIQ # 4

;Don not use the label 'IntVectorTable',
;The value of IntVectorTable is different with the address you think it may be.
;IntVectorTable
HandleEINT0 # 4
HandleEINT1 # 4
HandleEINT2 # 4
HandleEINT3 # 4
HandleEINT4_7 # 4
HandleEINT8_23 # 4
HandleRSV6 # 4
HandleBATFLT # 4
HandleTICK # 4
HandleWDT # 4
HandleTIMER0 # 4
HandleTIMER1 # 4
HandleTIMER2 # 4
HandleTIMER3 # 4
HandleTIMER4 # 4
HandleUART2 # 4
HandleLCD # 4
HandleDMA0 # 4
HandleDMA1 # 4
HandleDMA2 # 4
HandleDMA3 # 4
HandleMMC # 4
HandleSPI0 # 4
HandleUART1 # 4
HandleRSV24 # 4
HandleUSBD # 4
HandleUSBH # 4
HandleIIC # 4
HandleUART0 # 4
HandleSPI1 # 4
HandleRTC # 4
HandleADC # 4

END
　

Copyright©（版权所有）2003 PALaDiN（转载请注明出处）