verilog 练习题1

设计一个带控制端的逻辑运算电路，分别完成正整数的平方、立方和阶乘的运算

module test33(clk,n,result,reset); 

output[31:0] result; 
input[3:0] n; 
input reset,clk; 
reg[31:0] result; 
always @(posedge clk) //clk?????????? 
begin 
if(!reset) //reset?????? 
result<=0; 
end 
function [31:0] factorial; //????? 
input [3:0] operand; 
reg [3:0] index; 
input ctrl;
case(ctrl) 
1: factorial = n*n; //???? 
2: factorial = n*n*n; //???? 
default:  
begin 
factorial = operand ? 1 : 0; 
for(index=2;index<=5;index=index+1) 
factorial = index * factorial; 
end 
endcase
endfunction 
endmodule