Program Block-systemverilog

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systemverilog中的Program Block与module有些类似，但module是基于硬件思想，Program Block纯粹是为了仿真。如果不熟悉program,可以不用program.

The program block serves three basic purposes:

» It provides an entry point to the execution of testbenches.
» It creates a scope that encapsulates program-wide data.
» It provides a syntactic context that specifies scheduling in the Reactive region.

module test(...) int shared; // variable shared by programs p1 and p1
program p1; ...
endprogram
program p2;
...
endprogram // p1 and p2 are implicitly instantiated once in module testendmodule

Examp:

`timescale 1ns/1psclass frame_start;rand byte length = 64'habcdabc101023acd123;rand byte tag_frame_ma;byte Num;//octal numberinteger Tx_en;task frame();beginif ((length/Num) || (length > tag_frame_ma))$display ("\nReport the Tag frame error length = %d",length);else$display("\nReport Tag frame %d",length);endendtaskendclassprogram sim_top();frame_start new_frame;integer transmission_enable = 0;// Transmission of frame. Frame Tx include data encapulation and Media Access Managementtask transmit(integer transmission_enable);if (transmission_enable)$display("\n@%g, Frame is ready to transmit",$time);else$display("\n@%g, Frame is not ready now to transmit",$time);endtaskinitialbeginnew_frame = new;$display("*******--------*********--------********--------********");#1 transmit(transmission_enable);#1 transmission_enable = 1;#1 transmit(transmission_enable);#1 new_frame.frame();#1 new_frame.randomize();#1 $display("\n@%g, Transmit next frame now...", $time);#1 $display("\n*******--------*********--------********--------********");endendprogram

output:

# *******--------*********--------********--------********# # @1, Frame is not ready now to transmit# # @3, Frame is ready to transmit# # Report the Tag frame error length =   35# # @6, Transmit next frame now...# # *******--------*********--------********--------********

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