__get_cpu_architecture

/*read c0, Main ID Register (MIDR)

31             24    23     20   19            16   15                                4   3            0
Implementer    Variant    Architecture    Primary part number    Revision

Table    B3-21    Architecture codes
Bits [19:16]     Architecture
0x1                   ARMv4
0x2                   ARMv4T
0x3                   ARMv5 (obsolete)
0x4                   ARMv5T
0x5                   ARMv5TE
0x6                   ARMv5TEJ
0x7                   ARMv6
0xF                   Defined by CPUID scheme

*/

static int __get_cpu_architecture(void)
{
 int cpu_arch;

 if ((read_cpuid_id() & 0x0008f000) == 0) {

//bit19&bit[15:12] == 0-> MSB of architecture field & top four bits of the primary part number both are 0x0.
  cpu_arch = CPU_ARCH_UNKNOWN;
 } else if ((read_cpuid_id() & 0x0008f000) == 0x00007000) {

//MSB of architecture field is 0, top four bits of the primary part number are 0x7.
  cpu_arch = (read_cpuid_id() & (1 << 23)) ? CPU_ARCH_ARMv4T : CPU_ARCH_ARMv3;

/*If bit[23] is 1, the processor is an ARMv4T processor and bits[22:16] are an IMPLEMENTATION
DEFINED variant number. Bits[31:24,15:0] are as described for ARMv7.

If bit[23] is 0, the processor is an obsolete ARMv3 processor.

*/
 } else if ((read_cpuid_id() & 0x00080000) == 0x00000000) {

//MSB of architecture field is 0, upon Table B3-21 to find arch.
  cpu_arch = (read_cpuid_id() >> 16) & 7;
  if (cpu_arch)
   cpu_arch += CPU_ARCH_ARMv3;
 } else if ((read_cpuid_id() & 0x000f0000) == 0x000f0000) {
  unsigned int mmfr0;

  /* Revised CPUID format. Read the Memory Model Feature
   * Register 0 and check for VMSAv7 or PMSAv7 */

/* read Memory Model Feature Register 0 (ID_MMFR0)

PMSA support, bits [7:4]
Indicates support for a PMSA. Permitted values are:
0b0000 Not supported.
0b0001 Support for IMPLEMENTATION DEFINED PMSA.
0b0010 Support for PMSAv6, with a Cache Type Register implemented.
0b0011 Support for PMSAv7, with support for memory subsections. ARMv7-R profile.
When the PMSA support field is set to a value other than 0b0000 the VMSA support field
must be set to 0b0000.
VMSA support, bits [3:0]
Indicates support for a VMSA. Permitted values are:
0b0000 Not supported.
0b0001 Support for IMPLEMENTATION DEFINED VMSA.
0b0010 Support for VMSAv6, with Cache and TLB Type Registers implemented.
0b0011 Support for VMSAv7, with support for remapping and the access flag.
ARMv7-A profile.
When the VMSA support field is set to a value other than 0b0000 the PMSA support field
must be set to 0b0000.

*/
  asm("mrc p15, 0, %0, c0, c1, 4"
      : "=r" (mmfr0));
  if ((mmfr0 & 0x0000000f) >= 0x00000003 ||
      (mmfr0 & 0x000000f0) >= 0x00000030)
   cpu_arch = CPU_ARCH_ARMv7;
  else if ((mmfr0 & 0x0000000f) == 0x00000002 ||
    (mmfr0 & 0x000000f0) == 0x00000020)
   cpu_arch = CPU_ARCH_ARMv6;
  else
   cpu_arch = CPU_ARCH_UNKNOWN;
 } else
  cpu_arch = CPU_ARCH_UNKNOWN;

 return cpu_arch;
}