STM32F30X时钟初始化为HSI 64Mhz,并使用PLLCLK作为系统时钟

来源：互联网发布：c语言子程序调用实例编辑：程序博客网时间：2024/05/17 00:02

void SYSCLK_Config_HSI_64Mhz(void){__IO uint32_t StartUpCounter = 0, HSIStatus = 0;/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*//* Enable HSI */RCC->CR |= ((uint32_t)RCC_CR_HSION);/* Wait till HSI is ready and if Time out is reached exit */do{  HSIStatus = RCC->CR & RCC_CR_HSIRDY;  StartUpCounter++;  } while((HSIStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));if ((RCC->CR & RCC_CR_HSIRDY) != RESET){  HSIStatus = (uint32_t)0x01;}else{  HSIStatus = (uint32_t)0x00;}  if (HSIStatus == (uint32_t)0x01){  /* Enable Prefetch Buffer */  FLASH->ACR |= FLASH_ACR_PRFTBE;    /* Flash 2 wait state */  FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);  FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;     /* HCLK = SYSCLK */  RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;  /* PCLK2 = HCLK */  RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;    /* PCLK1 = HCLK */  RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;      /* Clear PLL Source [16] and Multiplier [21:18] bits */   RCC->CFGR &= ~(RCC_CFGR_PLLMULL | RCC_CFGR_PLLSRC);   /*  PLL configuration: PLLCLK = HSI / 2 * 16 = 64 MHz */  RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI_Div2 | RCC_CFGR_PLLMULL16);       /* Enable PLL */  RCC->CR |= RCC_CR_PLLON;    /* Wait till PLL is ready */  while((RCC->CR & RCC_CR_PLLRDY) == 0)  {  }    /* Select PLL as system clock source */  RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));  RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;     /* Wait till PLL is used as system clock source */  while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)  {  }}else{ /* If HSE fails to start-up, the application will have wrong clock    configuration. User can add here some code to deal with this error */}}

来自：http://blog.csdn.net/lan120576664?viewmode=contents

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