数字电路设计之VGA的字母显示的verilog实现

module vga_initials_top(mclk,btn,sw,hsync,vsync,red,green,blue    );input wire  mclk;input wire       btn;input wire [7:0] sw;output wire      hsync;output wire      vsync;output wire [2:0]red;output wire [2:0]green;output wire [1:0]blue;wire       clk,clk25,vidon;wire [9:0] hc,vc;wire [0:31]M;wire [3:0] rom_addr4;assign clr = btn;clkdiv U1(.mclk(mclk),.clr(clr),.clk25(clk25));vga_640x480 U2(.clk(clk25),.clr(clr),.hsync(hsync),.vsync(vsync),.hc(hc),.vc(vc),.vidon(vidon));vga_initial U3(.vidon(vidon),.hc(hc),.vc(vc),.M(M),.sw(sw),.rom_addr4(rom_addr4),.red(red),.green(green),.blue(blue));prom_DMH U4(.addr(rom_addr4),.M(M));endmodule

module clkdiv(mclk,clr,clk25    );input wire mclk;input wire clr;output wire clk25;//output wire clk48;reg  [24:0] q;always@(posedge mclk or posedge clr) beginif(clr)q <= 0;else q <= q + 1;endassign clk25 = q[1];endmodule

module vga_640x480(clk,clr,hsync,vsync,hc,vc,vidon);input wire clk;input wire clr;output reg  hsync;output reg          vsync;output reg   [9:0]  hc;output reg   [9:0]  vc;output reg          vidon;parameter hpixels = 10'b11001_00000; //琛屽儚绱犵偣=800parameter vlines = 10'b10000_01001;  //琛屾暟=521parameter hbp = 10'b001000_10000;//parameter hfp = 10'b11000_10000;parameter vbp =10'b00000_11111;parameter vfp = 10'b01111_11111;reg vsensable;  //enable for the vertical counter//琛屽悓姝ヤ俊鍙疯鏁板櫒路always@(posedge clk)  beginif(clr) hc <= 0;elsebeginif(hc == hpixels - 1) beginhc <= 0;vsensable <= 1;//enable teh vertical counter to increaseendelsebeginhc <= hc + 1;vsensable <= 0; //leave the vsenable offendendend//浜х敓hsync鑴夊啿//褰揾c涓~127鐨勬椂鍊欙紝琛屽悓姝ヤ俊鍙蜂负浣庣數骞always@(*) beginif(hc < 96)hsync <= 0;else hsync <= 1;end//鍦哄悓姝ヤ俊鍙疯鏁板櫒always@(posedge clk) beginif(clr)vc <= 0;else beginif(vsensable == 1) beginif(vc == vlines - 1)vc <= 0;else vc <= vc + 1;endendend//浜х敓vsync鑴夊啿//褰揾c涓鎴栬€鐨勬椂鍊欙紝鍦哄悓姝ヨ剦鍐蹭负浣庣數骞always@(*) beginif( vc < 2) vsync <= 0;elsevsync <= 1;endalways@(*) beginif((hc < hfp)&&(hc > hbp)&&(vc < vfp)&&(vc > vbp))vidon <= 1;else vidon <= 0;endendmodule

module vga_initial(vidon,hc,vc,M,sw,rom_addr4,red,blue,green    );input wire  vidon;input wire  [9:0]hc;input wire  [9:0]vc;input wire  [0:31]M;input wire  [7:0]sw;output wire [3:0]rom_addr4;output reg  [2:0]red;output reg  [2:0]green;output reg  [1:0]blue;parameter hbp = 10'b00100_10000;  //行显示后沊parameter vbp = 10'b00000_11111;  //场显示后沊parameter W = 32;parameter H = 16;wire [10:0]C1,R1,rom_addr,rom_pix;reg spriteon,R,G,B;assign C1 = {2'b00,sw[3:0],5'b00001};assign R1 = {2'b00,sw[7:4],5'b00001};assign rom_addr = vc - vbp - R1;assign rom_pix = hc - hbp - C1;assign rom_addr4 = rom_addr[3:0];//enable sprite video out when within the sprite regionalways@(*) beginif((hc >= C1 + hbp )&&(hc < C1 + hbp + W)&& (vc >= R1 + vbp)&&(vc <R1 + vbp + H))spriteon <= 1;elsespriteon <= 0;endalways@(*)  beginif((spriteon == 1)&&(vidon == 1))  beginR <= M[rom_pix];G <= M[rom_pix];B <= M[rom_pix];red <= {R,R,R};green <= {G,G,G};blue <= {B,B};endelse beginred <= 0;green <= 0;blue <= 0;endendendmodule

module prom_DMH(addr,M    );input wire [3:0] addr;output wire [0:31]M;wire [31:0]show = 32'h1234; reg [0:31]rom[0:15];parameter data0 = {8'b01111110,  //08'b10000001,  //18'b10111001,  //28'b10111001,  //38'b10111001,  //48'b10111001,  //58'b10111001,  //68'b10111001,  //78'b10111001,  //88'b10111001,  //98'b10111001,  //108'b10111001,  //118'b10111001,  //128'b10111001,  //138'b10000001,  //148'b01111110   //15};parameter data1 = {8'b00111000,  //08'b11111000,  //18'b00111000,  //28'b00111000,  //38'b00111000,  //48'b00111000,  //58'b00111000,  //68'b00111000,  //78'b00111000,  //88'b00111000,  //98'b00111000,  //108'b00111000,  //118'b00111000,  //128'b00111000,  //138'b00111000,  //148'b01111100   //15};parameter data2 = {8'b00111110,  //08'b11000001,  //18'b10000010,  //28'b00000010,  //38'b00000100,  //48'b00000100,  //58'b00000100,  //68'b00001000,  //78'b00110000,  //88'b00110000,  //98'b00100000,  //108'b00100000,  //118'b00100000,  //128'b01000000,  //138'b11000000,  //148'b11111111   //15};parameter data3 = {8'b01111110,  //08'b10000001,  //18'b00000010,  //28'b00000100,  //38'b00001000,  //48'b00010000,  //58'b00100000,  //68'b11000000,  //78'b11000000,  //88'b00100000,  //98'b00010000,  //108'b00001000,  //118'b00000100,  //128'b00000010,  //138'b10000001,  //148'b01111110   //15};parameter data4 = {8'b00000010,  //08'b00000100,  //18'b00001000,  //28'b00010000,  //38'b00110000,  //48'b01010000,  //58'b10010000,  //68'b11111111,  //78'b00010000,  //88'b00010000,  //98'b00010000,  //108'b00010000,  //118'b00010000,  //128'b00010000,  //138'b00010000,  //148'b00010000   //15};parameter data5 = {8'b11111111,  //08'b10000000,  //18'b10000000,  //28'b10000000,  //38'b10000000,  //48'b11110000,  //58'b00001000,  //68'b00000100,  //78'b00000010,  //88'b00000001,  //98'b00000010,  //108'b00000100,  //118'b00001000,  //128'b00010000,  //138'b00100000,  //148'b01000000   //15};parameter data6 = {8'b01111111,  //08'b01000000,  //18'b01000000,  //28'b01000000,  //38'b01000000,  //48'b01000000,  //58'b01000000,  //68'b01111111,  //78'b01000001,  //88'b01000001,  //98'b01000001,  //108'b01000001,  //118'b01000001,  //128'b01000001,  //138'b01000001,  //148'b01111111   //15};parameter data7 = {8'b01111111,  //08'b00000001,  //18'b00000001,  //28'b00000010,  //38'b00000010,  //48'b00000010,  //58'b00000100,  //68'b00000100,  //78'b00001000,  //88'b00001000,  //98'b00010000,  //108'b00010000,  //118'b00100000,  //128'b00100000,  //138'b01000000,  //148'b01000000   //15};parameter data8 = {8'b01111110,  //08'b01000010,  //18'b01000010,  //28'b01000010,  //38'b01000010,  //48'b01000010,  //58'b01000010,  //68'b01000010,  //78'b01111110,  //88'b01000010,  //98'b01000010,  //108'b01000010,  //118'b01000010,  //128'b01000010,  //138'b01000010,  //148'b01111110   //15};parameter data9 = {8'b01111111,  //08'b01000001,  //18'b01000001,  //28'b01000001,  //38'b01000001,  //48'b01000001,  //58'b01000001,  //68'b01111111,  //78'b00000001,  //88'b00000001,  //98'b00000001,  //108'b00000001,  //118'b00000001,  //128'b00000001,  //138'b00000010,  //148'b01111100   //15};parameter dataa = {8'b011111111,  //08'b000000001,  //18'b000000001,  //28'b000000001,  //38'b000000001,  //48'b000000001,  //58'b000000001,  //68'b000000001,  //78'b011111111,  //88'b010000001,  //98'b010000001,  //108'b010000001,  //118'b010000001,  //128'b010000001,  //138'b010000001,  //148'b011111110   //15};parameter datab = {8'b01000000,  //08'b01000000,  //18'b01000000,  //28'b01000000,  //38'b01000000,  //48'b01000000,  //58'b01100000,  //68'b01010000,  //78'b01001000,  //88'b01000100,  //98'b01000010,  //108'b01000001,  //118'b01000001,  //128'b01000010,  //138'b01000100,  //148'b01110000   //15};parameter datac = {8'b00000001,  //08'b00000010,  //18'b00000100,  //28'b00001000,  //38'b00010000,  //48'b00100000,  //58'b01000000,  //68'b01000000,  //78'b01000000,  //88'b00100000,  //98'b00010000,  //108'b00001000,  //118'b00001000,  //128'b00000100,  //138'b00000010,  //148'b00000001   //15};parameter datad = {8'b00000001,  //08'b00000001,  //18'b00000001,  //28'b00000001,  //38'b00000001,  //48'b00000001,  //58'b00000001,  //68'b00000001,  //78'b01111111,  //88'b01000001,  //98'b01000001,  //108'b01000001,  //118'b01000001,  //128'b01000001,  //138'b01000001,  //148'b01111111   //15};parameter datae = {8'b,  //08'b,  //18'b,  //28'b,  //38'b,  //48'b,  //58'b,  //68'b,  //78'b,  //88'b,  //98'b,  //108'b,  //118'b,  //128'b,  //138'b,  //148'b   //15};parameter dataf = {8'b00001111,  //08'b00010000,  //18'b00010000,  //28'b00010000,  //38'b00010000,  //48'b00010000,  //58'b00010000,  //68'b00010000,  //78'b11111111,  //88'b11111111,  //98'b00010000,  //108'b00010000,  //118'b00010000,  //128'b00010000,  //138'b00010000,  //148'b00111000   //15};parameter data = {32'b01000000000011000001101000000010,  //032'b11000001000011000001101000000010,  //132'b01000000100010100010101000000010,  //232'b01000000010010100010101000000010,  //332'b01000000001010100010101000000010,  //432'b01000000001010010010101000000010,  //532'b01000000001010010010101000000010,  //632'b01000000001010010010101111111110,  //732'b01000000001010001000101000000010,  //832'b01000000001010001000101000000010,  //932'b01000000001010001000101000000010,  //1032'b01000000001010001000101000000010,  //1132'b01000000010010000000101000000010,  //1232'b01000000100010000000101000000010,  //1332'b01000001000010000000101000000010,  //1432'b01000000000100000000101000000010   //15};integer i;/*initial beginfor(i = 0;i < 16;i= i+1)rom[i] = data[(511-32*i)-:32];end*///[0:31]rom[0:15];always@(*) beginfor(i = 0;i < 16;i= i+1)rom[i] = data[(511-32*i)-:32];endassign M = rom[addr];endmodule