一个32位DDS的可综合代码

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功能描述：
    累加器32位
    频率控制字27位，高位屏蔽，内部设置为0
    输出地址宽度11位，可带2k ROM

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------
entity DDS32 is
port(
    clock         :         in std_logic;
    FreqCtrl    :        in    std_logic_vector(26 downto 0);
    Address        :        out    std_logic_vector(10 downto 0);
    RD            :        out std_logic
    );
end;
-------------------------------------------------------
architecture behav of DDS32 is
    signal Bdata32     : std_logic_vector(31 downto 0);
    signal ACC        : std_logic_vector(31 downto 0);
begin
-------------------------------------
    Bdata32(26 downto 0)    <=    FreqCtrl;
    Bdata32(31 downto 27)    <=    "00000";
-------------------------------------
    process(clock)
    begin
        if clock'event and clock = '1' then
            ACC <= Bdata32 + ACC;
            Address <= ACC(31 downto 21);
        end if;
    end process;
-------------------------------------
    --Read signal--High available
    RD <= not clock;
end;

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