记录我的VHDL学习之路（二）

--/***************************************--** THIS FILE FOR FIR MODULE --** THIS IS A 18 ORDER DIRECT FIR    --** BY YANGHUIDONG--** DATE 20.3.2015  --***************************************TYPE MATRIX_COEFFICIENT IS ARRAY (16 DOWNTO  0) OF INTEGER ;CONSTANT H: MATRIX_COEFFICIENT:=(-86,34,-39,44,-48,52,-55,56,967,56,-55,52,-48,44,-39,34,-86); --17 BITS COEFFICIENTTYPE MATRIX_SEQUENCE IS ARRAY (32 DOWNTO  0) OF STD_LOGIC_VECTOR(11 downto 0) ;SIGNAL X: MATRIX_SEQUENCE;          --input 11 bits sequence ,tmp 33 numTYPE MATRIX_MIDDLE IS ARRAY (16 DOWNTO  0) OF INTEGER ;  --define 17 tmp value SIGNAL P: MATRIX_MIDDLE;SIGNAL SUM:INTEGER;**********************************************************************************    PROCESS (MCLK)    BEGIN        IF MCLK'EVENT AND MCLK='1' THEN            IF RST='1' THEN                X <= (OTHERS => "000000000000"); 一维数组全部置0 ，vector类型“12个0”--              FOR j IN 0 TO 32 LOOP      --33 times set '0'  loop 置0；--                  X(j)<="000000000000";  --12 bits --              END LOOP;--             X <= (OTHERS =>(OTHER=> "000000000000")); 二维数组全部置0            ElSE                X(0)<=BIN;                       FOR i IN 1 TO 32 LOOP                        X(i)<=X(i-1);   --整体向右移位                    END LOOP;                            END IF;        END IF;    END PROCESS;