Error during bitstream generation

Partially routed net

Common issues to look for

• Carry Chains that are not aligned and BX pin not available for route-thru

• Too many global signals driving non-clock pins in a tile

• Differential I/O Pair not placed together in paired sites

• Clock Region over populated with too many global nets. No clock spines unused.

• Directed Route blocking switchbox route path to pin.

• BUFIO or BUFR with loads not constrained within reach

Method:

Open the implemented design in Vivado and find the list of unrouted nets using Find (refer to below screenshot). Highlight the unrouted nets and then zoom in on them to examine the pin connectivity involved.

if there is unconnected interface in the block design could case this problem.

IO placement is infeasible

This error can occur in 2 situations:

1) the design uses more I/Os than there are available in the selected device and package combination
Review the amount of toplevel ports used and if the correct device and package was selected

2) There are more toplevel ports than there are available in the device and package combination, but not all are used.
Vivado Synthesis did not correctly optimize away all unused toplevel ports.
This is a known issue that will be resolved in a future version of Vivado.