Makefile
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Makefile
Makefile is used to tell the compiler how to compile and link the source file.
structure
Makefile is organized by some rules:
target:prerequisites
commands
target stands for a object file or a exxcutable file,sometime it just stands for label.
prerequisites stand for the files that used to produce the target
commands stand for shell commands
this rule is used to describe the dependency relation between target and prerequisites.for example,if everything in prerequisites is is not modified,when you execute the make command,nothing happened.if some files in prerequisites are modified lately,when you execute the make command.the modified files will be compiled agian,then linked.
ob1.o:ob1.c ob1.h
g++ -c ob1.c
ob2.o:ob2.c ob2.h
g++ -c ob2.c
ob3.o:ob3.c ob3.h
g++ -c ob3.c
main:ob1.o ob2.o ob3.o
g++ -o main ob1.o ob2.o ob3.o
the symbol in Makefile
$@ : the target
$^ : the prerequisites
$< : the first file in prerequisites
/ : line feed
so when you see Makefile lines like:
main: ob1.o ob2.o ob3.o
g++ -o
@ ^
it’s means that the compiler linked all the object files to produce a executable file named main.
introduce to g++
options
-c : produce a object file
-Idir :inlcude head dir,the compiler is going to find the head file in the path you select,if not find ,the compiler will find the head file in a system default path.
-Ldir:the options tell the compiler where to find the libary that used to compiler the source.
-llibrary: the library that used to compile.
-Wall : tell the compiler to output all the warning message
-w : tell the compiler to close all the warning message
-Dmacro=defn :define a macro
-ON,N=0,1,2,3 when you need debug the source code,you need to disable the compiler’s optimization function by adding a option -O0,actully ,there is four level optimization option -O0,1,2,3,-O0 tell the compiler disable the optimization function ,and the -ON,N=1,2,3 tell the comipler optimize even more.
-g this flag tells comipler to keep the debug infomation.it’s necessary for the debug step.
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