Fast Median Filtering Based on FPGA

ALGORITHM

Step 1：
Maximum Group ：Max0 = max[P0，P3，P6]，Max1 = max[P1，P4，P7]，Max2 = max[P2，P5，P8]
Median Group ： Med0 = med[P0，P3，P6]，Med1 = med[P1，P4，P7]， Med2 = med[P2，P5，P8]
Minimum Group ：Min0 = Min[P0，P3，P6]，Min1 = Min[P1，P4，P7]，Min2 = max[P2，P5，P8]

Step 2：
s0 = Minimum{ Maximum Group }
s1 = Median{Median Group}
s2 = Maximum{Minimum Group}

Step 3： Result = Median{s0, s1, s2}
From here, we find we need 19 comparison, but quick sort need 9log9 times，bubble sort needs 9(9−1)2=36 times comparisons. What’s more, using pipeline we can divide the whole process into three cycles.

IMPLEMENTATION

module Test(    clk,    rst,    MedianResult);    input wire        clk;    input wire        rst;    output wire [31:0]MedianResult;    wire [31:0]BlockData[8:0];    assign BlockData[8] = 12;    assign BlockData[7] = 4;    assign BlockData[6] = 16;    assign BlockData[5] = 67;    assign BlockData[4] = 78;    assign BlockData[3] = 5;    assign BlockData[2] = 102;    assign BlockData[1] = 2;    assign BlockData[0] = 209;    FastMedianFiltering Test( BlockData[8], BlockData[7], BlockData[6], BlockData[5], BlockData[4],                              BlockData[3], BlockData[2], BlockData[1], BlockData[0], MedianResult , clk, rst);endmodulemodule FastMedianFiltering(    BlockData8,    BlockData7,    BlockData6,    BlockData5,    BlockData4,    BlockData3,    BlockData2,    BlockData1,    BlockData0,    MedianResult,    clk,    rst    );    input wire  [31:0]BlockData8;    input wire  [31:0]BlockData7;    input wire  [31:0]BlockData6;    input wire  [31:0]BlockData5;    input wire  [31:0]BlockData4;    input wire  [31:0]BlockData3;    input wire  [31:0]BlockData2;    input wire  [31:0]BlockData1;    input wire  [31:0]BlockData0;    output wire [31:0]MedianResult;    input wire         clk;    input wire        rst;    wire [31:0]step1[8:0];    wire [31:0]step2[8:0];    wire [31:0]step3[2:0];    // Step 1    OperatorToGetMaxMedAndMin Step1_0(BlockData8, BlockData7, BlockData6, step1[8], step1[7], step1[6], clk, rst);    OperatorToGetMaxMedAndMin Step1_1(BlockData5, BlockData4, BlockData3, step1[5], step1[4], step1[3], clk, rst);    OperatorToGetMaxMedAndMin Step1_2(BlockData2, BlockData1, BlockData0, step1[2], step1[1], step1[0], clk, rst);    // Step 2    OperatorToGetMaxMedAndMin Step2_Maximum(step1[8], step1[5], step1[2], step2[8], step2[7], step2[6], clk, rst);      OperatorToGetMaxMedAndMin Step2_Median(step1[7], step1[4], step1[1], step2[5], step2[4], step2[3], clk, rst);      OperatorToGetMaxMedAndMin Step2_Minimum(step1[6], step1[3], step1[0], step2[2], step2[1], step2[0], clk, rst);      // Step 3    OperatorToGetMaxMedAndMin Step3_Median(step2[2], step2[4], step2[6], step3[2], step3[1], step3[0], clk, rst);     assign MedianResult = step3[1];endmodule module OperatorToGetMaxMedAndMin(    InData2,    InData1,    InData0,    OutData2,    OutData1,    OutData0,    clk,    rst    );    input wire [31:0]InData2;    input wire [31:0]InData1;    input wire [31:0]InData0;    output reg [31:0]OutData2;    output reg [31:0]OutData1;    output reg [31:0]OutData0;    input wire        clk;    input wire       rst;    always@(posedge clk, negedge rst)    begin        if(!rst)            begin                OutData2 <= 32'b0;                OutData1 <= 32'b0;                OutData0 <= 32'b0;            end        else if((InData2 > InData1) && (InData2 > InData0) && (InData0 > InData1))            begin                   OutData2 <= InData2;                OutData1 <= InData0;                OutData0 <= InData1;            end        else if((InData2 > InData1) && (InData0 > InData2))              begin                   OutData2 <= InData0;                OutData1 <= InData2;                OutData0 <= InData1;            end        else if((InData2 > InData0) && (InData1 > InData2))              begin                   OutData2 <= InData1;                OutData1 <= InData2;                OutData0 <= InData0;            end        else if((InData1 > InData2) && (InData0 > InData2) && (InData0 > InData1))              begin                   OutData2 <= InData0;                OutData1 <= InData1;                OutData0 <= InData2;            end        else if((InData1 > InData2) && (InData0 > InData2) && (InData1 > InData0))              begin                   OutData2 <= InData1;                OutData1 <= InData0;                OutData0 <= InData2;            end        else            begin                   OutData2 <= InData2;                OutData1 <= InData1;                OutData0 <= InData0;            end    endendmodule