【西西学FPGA】Lesson12

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课堂内容：
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module pic(
        input wire sclk,
        input wire s_rst_n,
        
        output reg h_sync,
        output reg v_sync,
        output reg [2:0] vga_red,
        output reg [2:0] vga_green,
        output reg [1:0] vga_blue
        );
        
        reg [9:0] h_sync_cnt;
        reg [9:0] v_sync_cnt;
        reg clk_25mhz;
        reg [25:0] clk_cnt;
        
        reg [9:0] x;
        reg [9:0] y;
        reg x_flag;
        reg y_flag;

parameter
        H_SYNC = 10'd799,
        V_SYNC = 10'd524;
        
////clk_cnt //1s信号
//always@(posedge sclk or negedge s_rst_n)
// if(!s_rst_n)
// clk_cnt <= 26'd0;
// else if (clk_cnt == CLK_CNT)
// clk_cnt <= 26'd0;
// else
// clk_cnt <= clk_cnt + 1'b1;
//
//to ram
        reg [15:0] rdaddress;
           
        reg wren;
        wire [7:0] q;
//rdaddress
always@(posedge clk_25mhz or negedge s_rst_n)
        if(!s_rst_n)
                rdaddress <= 16'd0;
        else if (rdaddress == 16'd39999)
                rdaddress <= 16'd0;
        else if ((h_sync_cnt <= 10'd342 + x )&&(h_sync_cnt >= 10'd143 + x )&&(v_sync_cnt <= 10'd233 + y )&&(v_sync_cnt >= 10'd34 + y ))
                rdaddress <= rdaddress + 1'b1;
//wren
always@(posedge sclk or negedge s_rst_n)
        if(!s_rst_n)
                wren <= 1'b0;
        else
                wren <= 1'b0;


//x
always@(posedge clk_25mhz or negedge s_rst_n)
        if(!s_rst_n)
                x <= 10'd0;
        else if ((x_flag == 1'b0)&&(h_sync_cnt == 10'd799)&&(v_sync_cnt == 10'd524))
                x <= x + 1'b1;
        else if ((x_flag == 1'b1)&&(h_sync_cnt == 10'd799)&&(v_sync_cnt == 10'd524))
                x <= x - 1'b1;
//y
always@(posedge clk_25mhz or negedge s_rst_n)
        if(!s_rst_n)
                y <= 10'd0;
        else if ((y_flag == 1'b0)&&(h_sync_cnt == 10'd799)&&(v_sync_cnt == 10'd524))
                y <= y + 1'b1;
        else if ((y_flag == 1'b1)&&(h_sync_cnt == 10'd799)&&(v_sync_cnt == 10'd524))
                y <= y - 1'b1;
// x_flag
always@(posedge clk_25mhz or negedge s_rst_n )
        if(!s_rst_n)
                x_flag <= 1'b0;
        else if(x ==10'd438)
                x_flag <= 1'b1;
        else if (x == 10'd1)
                x_flag <= 1'b0;
//y_flag
always@(posedge sclk or negedge s_rst_n )
        if(!s_rst_n)
                y_flag <= 1'b0;
        else if(y ==10'd278)
                y_flag <= 1'b1;
        else if (y == 10'd1)
                y_flag <= 1'b0;

//clk_25mhz;
always@(posedge sclk or negedge s_rst_n)
        if(!s_rst_n)
                clk_25mhz <= 1'b1;
        else
                clk_25mhz <= ~clk_25mhz;
                
//h_sync_cnt;
always@(posedge clk_25mhz or negedge s_rst_n)
        if(!s_rst_n)
                h_sync_cnt <= 10'd0;
        else if (h_sync_cnt == H_SYNC)
                h_sync_cnt <= 10'd0;
        else
                h_sync_cnt <= h_sync_cnt + 1'b1;

//v_sync_cnt;
 always@(posedge clk_25mhz or negedge s_rst_n)
        if(!s_rst_n)
                v_sync_cnt <= 10'd0;
        else if ((v_sync_cnt == V_SYNC)&&(h_sync_cnt == H_SYNC))
                v_sync_cnt <= 10'd0;
        else if (h_sync_cnt == H_SYNC)
                v_sync_cnt <= v_sync_cnt + 1'b1;

//h_sync,
always@(posedge clk_25mhz or negedge s_rst_n)
        if(!s_rst_n)
                h_sync <= 1'b1;
        else if (h_sync_cnt <= 10'd95)
                h_sync <= 1'b0;
        else
                h_sync <= 1'b1;
                
//v_sync,
always@(posedge clk_25mhz or negedge s_rst_n)
        if(!s_rst_n)
                v_sync <= 1'b1;
        else if (v_sync_cnt <= 10'd1)
                v_sync <= 1'b0;
        else
                v_sync <= 1'b1;
                  
//vga_red,
//vga_green,
//vga_blue
always@(posedge clk_25mhz or negedge s_rst_n)
        if(!s_rst_n)
                {vga_red,vga_green,vga_blue} <= 8'b0;
                else if ((h_sync_cnt <= (10'd342 + x))&&(h_sync_cnt >= (10'd143+ x))&&(v_sync_cnt <= (10'd233 + y))&&(v_sync_cnt >= (10'd34 + y)))
                         {vga_red,vga_green,vga_blue}<= q;
                else if((v_sync_cnt <= 10'd514)&&(v_sync_cnt > 10'd 354)&&(h_sync_cnt <= 10'd783)&&(h_sync_cnt >= 10'd143))
                              {vga_red,vga_green,vga_blue}<= 8'b00000011;
                else if((v_sync_cnt <= 10'd354)&&(v_sync_cnt > 10'd 194)&&(h_sync_cnt <= 10'd783)&&(h_sync_cnt >= 10'd143))
                              {vga_red,vga_green,vga_blue}<= 8'b00011100;
                else if((v_sync_cnt <= 10'd194)&&(v_sync_cnt > 10'd 34)&&(h_sync_cnt <= 10'd783)&&(h_sync_cnt >= 10'd143))
                              {vga_red,vga_green,vga_blue}<= 8'b11100000;
                
        else
                {vga_red,vga_green,vga_blue} <= 8'b00000000;
                
ram_8x200x200 ram_8x200x200_inst (
        .clock ( clk_25mhz ),
        .rdaddress ( rdaddress ),
        .wren ( wren ),
        
        .q ( q )
        );
                              
endmodule
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matlab；
clc;//清屏
clear all;//清除所有内容
RGB_data = imread('aaa.jpg');//读取某图片的RGB数据，会生成三个二维数组，分别是8位的 RGB的值
R_data = RGB_data(:,:,1);//读取红的RBG值
G_data = RGB_data(:,:,2);
B_data = RGB_data(:,:,3);
[ROW,COL] = size(R_data);//size为函数，计算数组的大小
outdata = zeros(1,ROW*COL);//建立一个一维数组，从1 到 ROW*COL

for r = 1:ROW//for 循环，将对应的二维数组生成一维数组
    for c = 1:COL
        outdata((r-1)*COL+c) = bitand(R_data(r,c),224) + bitshift(bitand(G_data(r,c),224),-3) + bitshift(bitand(B_data(r,c),192),-6);
    end
end

miffile('outdata.mif',outdata,8,ROW*COL);//生成mif文件，数据位宽 ，数据个数

fid = fopen('aaa.txt','w+'); //打开aaa.TXT文件，w+ 表示在保留原来数据的基础上写数据
for i = 1:ROW*COL
    fprintf(fid,'%02x ',outdata(i));
end
fclose(fid);
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总结：
1 数值计算准备
2 减少中间变量


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课后作业：
uart+ram+fpga+vga