s5pv210 datasheet_system_BUS

1 BUS CONFIGURATION
1.1 OVERVIEW OF BUS CONFIGURATION
This chapter describes the bus configuration in S5PV210.
1.1.1 AXI INTERCONNECT
S5PV210 consists of 12 high-performance AXI interconnect. The role of AXI interconnect is to interconnect bus
masters to bus slaves.

1.1.1 AXI互连

S5PV210由12高性能 AXI 互连。AXI互连的作用是互连总线到隶属于总线的从设备。

1.1.1.1 Key Features of AXI Interconnect

The key features of AXI interconnect include:
• Quality of Service
The Quality of Service (QoS) scheme tracks the number ofoutstanding transactions. When a specified
number is reached, it permits transactions from specified masters only. This scheme only provides support for
slaves that have a combined acceptance capability such as the Dynamic Memory Controller (DMC).
The QoS scheme has no effect until the AXI interconnect matrix calculates the following:
At a particular Master Interface (MI), there are a number of outstanding transactions equal to the value stored in
QoS tidemark.

服务质量

服务质量（服务质量）计划跟踪优秀交易的数量。当指定的

数量达到了，它只允许指定的主设备的传输。此方案只提供支持

有一个联合验收能力如动态内存控制器（DMC）的从设备。

QoS方案没有影响到互连矩阵计算如下：

在一个特定的主界面（MI），有一个优秀的交易数量相等的值存储在QoS的峰值。

It then accepts transactions only from slave ports specified in the QoS access control. This restriction remains

until the number of outstanding transactions is again less than the value stored in QoS tidemark.

Figure 1-1 shows the implementation for an interconnect supporting two masters and one slave.

然后，它只接受来自于服务质量访问控制中的从属端口的事务处理。这种限制是

直到优秀的交易数量低于存储QoS商标的价值。

图1-1显示互连支持两个主设备和一个从设备的实现。

2CORESIGHT
2.1 CORESIGHT SYSTEM OVERVIEW
2.1.1 ABOUT CORESIGHT SYSTEMS GENERALS
CoreSight systems provide the entire infrastructure required to debug, monitor, and optimize the performance of a
complete System on Chip (SoC) design.

2 coresight

2.1 coresight系统概述

2.1.1关于coresight系统将军

coresight系统提供调试，监控所需的完整的基础设施，优化了完整的片上系统设计的性能。

There are historically three main ways of debugging an ARM processor based SoC:
在历史上，有三种主要的方法是调试一个基于ARM处理器的片上系统：

• Conventional JTAG debug. This is invasive debug with the core halted using:
− Breakpoints and watchpoints to halt the core on specific activity
− A debug connection to examine and modify registers and memory and provide single-step execution.
• Conventional monitor debug. This is invasive debug with the core running using a debug monitor that resides
in memory.

•常规JTAG调试。这是挂起系统核心使用的入侵调试用：

−停止特定活动的核心设置断点和观察点

−调试连接检查和修改寄存器和内存，提供单步执行。

常规监控调试。这是入侵调试的核心运行使用一个驻留在内存中的调试监视器。

• Trace. This is non-invasive debug with the core running at full speed using:
− Collection of information on instruction execution and data transfers
− Delivery off-chip in real-time
− Tools to merge data with source code on a development workstation for later analysis.

•跟踪。这是核心运行在全速使用中的无创调试的：

−信息收集指令执行和数据传输

−交付芯片实时

−工具合并数据供以后分析工作站上开发的源代码。

3ACCESS CONTROLLER (TZPC)
3.1 OVERVIEW OF ACCESS CONTROLLER (TZPC)
The TrustZone Protection Controller (TZPC) is an AMBA-compliant, tested, and licensed by ARM Limited. 

TrustZone保护控制器（tzpc）是一个AMBA兼容测试，由ARM有限公司授权。

The TZPC provides a software interface to the protection bits in a secure system in a TrustZone design. It provides
system flexibility that enables to configure different areas of memory as secure or non-secure.
The S5PV210 comprises of four TZPC.

这个tzpc提供了在信任区设计在一个安全的系统保护位的软件界面。它提供了

系统的灵活性，可以配置不同领域的内存安全或不安全。S5PV210包括四tzpc。

3.1.1 KEY FEATURES OF ACCESS CONTROLLER (TZPC)
Protection bits: This enables you to program maximum 32 areas of memory as secure or non-secure
Secure region bits: This enables you to split an area of internal RAM into both secure and non-secure regions
The Access Controller includes AMBA APB system interface

接入控制器3.1.1主要特点（tzpc）

保护位：这使您可以最大限度地保护内存的32个领域的安全或不安全

安全区域位：这使您可以将内部的内存区域拆分为安全和非安全区域

访问控制器包括AMBA APB系统接口