[zynq] zynq7000开发流程之仿真TestBench

工具：vivado、notepad++ (设置成Encode in ANSI，确保中文不乱码)

目标：基本常用的TB激励，vivado提供的激励

一般TB结构都比较简单，module不需要外部接口信号。

1、先将被测DUT实例化，定义dut的接口变量。

a)  站在TB的角度，输出信号定义reg（即dut的输入信号），TB的输入信号定义wire（即dut的输出信号），inout接口必须定义成wire。

b) 设计中是外接bram模块的，这里用数组模拟ram，定义： reg [7:0] mem [0:8191]; ，大小8KB，后面即地址[addr]。

2、时钟、复位初始化

这里仿真单位都是1ns，时钟一直有，启动50ns后释放reset。

initial /* clock gen */beginclk = 0;forever #10 clk = ~clk;//20ns 50mhzendinitial /* reset gen */beginrst_n = 0;#50rst_n = 1;end

3、内存初始化：前面256字节存储从0到255，4400开头的地址存命令字。

integer i;initial /* ram memory data */begin//initial datafor(i=0; i<255; i=i+1)mem[i] = i;//head infomem[4400] = 8'h00; //CMD1mem[4401] = 8'h30; //CMD2mem[4402] = 8'h70; //70Hmem[4403] = 8'h00; //feedbackmem[4404] = 8'h0F; //ADDR1mem[4405] = 8'h00; //ADDR2mem[4406] = 8'h0F; //ADDR3mem[4407] = 8'h00; //ADDR4mem[4408] = 8'h0F; //NUM1mem[4409] = 8'h00; //NUM2end

4、下面这段TB代码的功能是从SRAM读出数据，经过用户RTL代码后，送入到nand flash里面。

sram和nand是TB需要描述模拟的器件。写命令、写地址、写数据、等待busy/ready，写70H命令回读写成功状态。

关注nand_we_n上升沿时配合信号和数据是否正确，以及nand_rb_n状态。

`timescale 1ns/1ns/****************************************** * * this module is just for write nand * ******************************************/module tb_controller();wire nand_cle ;wire nand_ale ;wire nand_we_n;wire nand_re_n;wire nand_ce_n;wire nand_wp_n;reg  nand_rb_n; //busywire [7:0] nand_io ; //inoutwire ram_clk ;wire ram_en  ;wire ram_we  ;wire [12:0] ram_addr;wire [7:0] ram_din  ;reg  [7:0] ram_dout ;reg  clk;reg  rst_n;reg  fulfil;wire accomplish;wire out_led;/****************************************** * * global signals * ******************************************/ initial /* clock gen */beginclk = 0;forever #10 clk = ~clk;//20ns 50mhzendinitial /* reset gen asyn */beginrst_n = 0;#50rst_n = 1;endinitial /* fulfil trigger -> */beginfulfil = 0;#100fulfil =1;end/****************************************** * * SRAM simulation * ******************************************/ reg [7:0] mem_ram [0:8191];integer addr_ram;initial /* ram mem_ramory data */begin//initial datafor(addr_ram=0; addr_ram<255; addr_ram=addr_ram+1)mem_ram[addr_ram] = addr_ram;//head infomem_ram[4400] = 8'h80; //CMD1mem_ram[4401] = 8'h10; //CMD2mem_ram[4402] = 8'h70; //70Hmem_ram[4403] = 8'h00; //feedbackmem_ram[4404] = 8'h0F; //ADDR1mem_ram[4405] = 8'h00; //ADDR2mem_ram[4406] = 8'h0F; //ADDR3mem_ram[4407] = 8'h00; //ADDR4mem_ram[4408] = 8'h0F; //NUM1mem_ram[4409] = 8'h00; //NUM2endalways @(posedge ram_clk)beginif(ram_we==0) //data outbeginram_dout <= mem_ram[ram_addr];endelsebeginram_dout <= 8'hzz;endend/****************************************** * 模块：NAND simulation * 数据存到文件或数组中 * 按接收顺序存 ******************************************/reg [7:0] mem_nand[0:4351];reg [12:0] addr_nd;reg ask_70H;initialbegin /* busy time */addr_nd = 12'b0;ask_70H = 0;end/* 上升沿写入数据 */always @(posedge nand_we_n)beginif(nand_ce_n==0 && nand_cle==1 && nand_ale==0)begin //cmd //也可以参数固定地址mem_nand[addr_nd] = nand_io;addr_nd = addr_nd + 1;endelse if(nand_ce_n==0 && nand_cle==0 && nand_ale==1)begin //addrmem_nand[addr_nd] = nand_io;addr_nd = addr_nd + 1;endelse if(nand_ce_n==0 && nand_re_n==1)begin //data inmem_nand[addr_nd] = nand_io;addr_nd = addr_nd + 1;endelse begin //wrong operation$display("%t\t pls check wrong state below:",$time);$display("\t nand_ce_n=%b,nand_cle=%b,nand_ale=%b,nand_we_n=%b,nand_re_n=%b",nand_ce_n,nand_cle,nand_ale,nand_we_n,nand_re_n);endendalways @(posedge nand_we_n) /* nand_r/b# */beginif(nand_ce_n==0 && nand_cle==1 && nand_ale==0 && nand_io==8'h10)beginnand_rb_n = 0;#500 //busy timenand_rb_n = 1;endelsebeginnand_rb_n = 1;endendalways @(posedge nand_we_n or negedge nand_re_n) /* 70H feedback */beginif(nand_ce_n==0 && nand_cle==1 && nand_ale==0 && nand_io==8'h70)beginask_70H = 1;endelse if(ask_70H==1 && nand_re_n==0)begin //70H后RE有效 反馈statusmem_nand[addr_nd] = 8'h55; //ask_70H = 0;endelsebegin//endendinitial /* monitor */begin$monitor("%t\t fulfil=%b", $time, fulfil);$monitor("%t\t nand_rb_n=%b", $time, nand_rb_n);end/****************************************** * * DUT instantiation * ******************************************/nand_controller dut(/* nand side */.nand_cle  ( nand_cle ),.nand_ale  ( nand_ale ),.nand_we_n ( nand_we_n),.nand_re_n ( nand_re_n),.nand_ce_n ( nand_ce_n),.nand_wp_n ( nand_wp_n),.nand_rb_n ( nand_rb_n),.nand_io   ( nand_io  ),/* ram <-> nand */.ram_clk  ( ram_clk ),.ram_en   ( ram_en  ),.ram_we   ( ram_we  ),.ram_addr ( ram_addr),.ram_din  ( ram_din ),.ram_dout ( ram_dout), /* global signals */.clk             ( clk ),.rst_n           ( rst_n ),.fulfil_ddr_ram  ( fulfil ),.accomplish_nand ( accomplish),/* led: idle run err */.out_led ( out_led ));endmodule