IC 设计流程

Step 1: Prepare an Requirement Specification

Step 2: Create an Micro-Architecture Document.

Step 3: RTL Design & Development of IP's

Step 4: Functional verification all the IP's/Check whether the RTL is free fromLinting Errors/Analyze whether the RTL is Synthesis friendly.Step 4a: Perform Cycle-based verification(Functional) to verify the protocolbehaviour of the RTLStep 4b: Perform Property Checking , to verify the RTL implementation and thespecification understanding is matching.

Step 5: Prepare the Design Constraints file (clockdefinitions(frequency/uncertainity/jitter),I/O delay definitions, Output pad loaddefinition, Design False/Multicycle-paths) to perform Synthesis, usually called as anSDC synopsys_constraints, specific to synopsys synthesis Tool (design-compiler)

Step 6: To Perform Synthesis for the IP, the inputs to the tool are (library file(forwhich synthesis needs to be targeted for, which has the functional/timing informationavailable for the standard-cell library and the wire-load models for the wires based onthe fanout length of the connectivity), RTL files and the Design Constraint files, Sothat the Synthesis tool can perform the synthesis of the RTL files and map andoptimize to meet the design-constraints requirements. After performing synthesis, as apart of the synthesis flow, need to build scan-chain connectivity based on theDFT(Design for Test) requirement, the synthesis tool (Test-compiler), builds thescan-chain.

7: Check whether the Design is meeting the requirements(Functional/Timing/Area/Power/DFT) after synthesis.

Step 7a: Perform the Netlist-level Power Analysis, to know whether the design ismeeting the power targets.

Step 7b: Perform Gate-level Simulation with the Synthesized Netlist to check whetherthe design is meeting the functional requirements.

Step 7c: Perform Formal-verification between RTL vs Synthesized Netlist to confirmthat the synthesis Tool has not altered the functionality.

Step 7d: Perform STA(Static Timing Analysis) with the SDF(Standard Delay Format)file and synthesized netlist file, to check whether the Design is meeting thetiming-requirements.

Step 7e: Perform Scan-Tracing , in the DFT tool, to check whether the scan-chain isbuilt based on the DFT requirement.

Step 8: Once the synthesis is performed the synthesized netlist file(VHDL/Verilogformat) and the SDC (constraints file) is passed as input files to the Placement andRouting Tool to perform the back-end Actitivities.

Step 9: The next step is the Floor-planning, which means placing the IP's based on theconnectivity,placing the memories, Create the Pad-ring, placing thePads(Signal/power/transfer-cells(to switch voltage domains/Corner pads(properaccessibility for Package routing), meeting the SSN requirements(SimultaneousSwitching Noise) that when the high-speed bus is switching that it doesn't create anynoise related acitivities, creating an optimised floorplan, where the design meets theutilization targets of the chip.

Step 9a : Release the floor-planned information to the package team, to perform thepackage feasibility analysis for the pad-ring .

Step 9b: To the placement tool, rows are cut, blockages are created where the tool isprevented from placing the cells, then the physical placement of the cells is performedbased on the timing/area requirements.The power-grid is built to meet thepower-target's of the Chip .

Step 10: The next step is to perform the Routing., at first the Global routing andDetailed routing, meeting the DRC(Design Rule Check) requirement as per thefabrication requirement.

Step 11: After performing Routing then the routed Verilog netlist, standard-cellsLEF/DEF file is taken to the Extraction tool (to extract the parasitics(RLC) values ofthe chip in the SPEF format(Standard parasitics Exchange Format), and the SPEF fileis generated.

Step 12: Check whether the Design is meeting the requirements(Functional/Timing/Area/Power/DFT/DRC/LVS/ERC/ESD/SI/IR-Drop) afterPlacement and Routing step.

Step 12a: Perform the Routed Netlist-level Power Analysis, to know whether thedesign has met the power targets.

Step 12b: Perform Gate-level Simulation with the routed Netlist to check whether thedesign is meeting the functional requirement .

Step 12c: Perform Formal-verification between RTL vs routed Netlist to confirm thatthe place & route Tool has not altered the functionality.

Step 12d: Perform STA(Static Timing Analysis) with the SPEF file and routed netlistfile, to check whether the Design is meeting the timing-requirements.

Step 12e: Perform Scan-Tracing , in the DFT tool, to check whether the scan-chain isbuilt based on the DFT requirement, Peform the Fault-coverage with the DFT tool andGenerate the ATPG test-vectors.

Step 12f: Convert the ATPG test-vector to a tester understandable format(WGL)Step 12g: Perform DRC(Design Rule Check) verfication called asPhysical-verification, to confirm that the design is meeting the Fabricationrequirements.

Step 12h: Perform LVS(layout vs Spice) check, a part of the verification which takesa routed netlist converts to spice (call it SPICE-R) and convert the Synthesizednetlist(call it SPICE-S) and compare that the two are matching.

Step 12i : Perform the ERC(Electrical Rule Checking) check, to know that the designis meeting the ERC requirement.

Step 12j: Perform the ESD Check, so that the proper back-to-back diodes are placedand proper guarding is there in case if we have both analog and digital portions in ourChip. We have seperate Power and Grounds for both Digital and Analog Portions, toreduce the Substrate-noise.

Step 12k: Perform seperate STA(Static Timing Analysis) , to verify that theSignal-integrity of our Chip. To perform this to the STA tool, the routed netlist andSPEF file(parasitics including coupling capacitances values), are fed to the tool. Thischeck is important as the signal-integrity effect can cause cross-talk delay andcross-talk noise effects, and hinder in the functionality/timing aspects of the design.

Step 12l: Perform IR Drop analysis, that the Power-grid is so robust enough towith-stand the static and dynamic power-drops with in the design and the IR-drop iswith-in the target limits.

Step 13: Once the routed design is verified for the design constraints, then now thenext step is chip-finishing activities (like metal-slotting, placing de-coupling caps).

Step 14: Now the Chip Design is ready to go to the Fabrication unit, release fileswhich the fab can understand, GDS file.

Step 15: After the GDS file is released , perform the LAPO check so that the databasereleased to the fab is correct.

Step 16: Perform the Package wire-bonding, which connects the chip to the Package.

Step 5: Prepare the Design Constraints file (clock definitions(frequency/uncertainity/jitter),I/O
delay definitions, Output pad load definition, Design False/Multicycle-paths) to perform Synthesis,
usually called as an SDC synopsys_constraints, specific to synopsys synthesis Tool
(design-compiler)