vhdl 等占空比四分频

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity clk_div is    

port(clk:in std_logic;          clk_div4,clk_div2:out std_logic);

end clk_div;

architecture rtl of clk_div is signal count:std_logic_vector(1 downto 0 );

begin    

process(clk)    

begin       

if(clk'event and clk ='1')then           

if(count="11")then              

count<=(others=>'0');           

else              

count<=count+1;           

end if;       

end if;

end process;

clk_div4 <= not count(1);

end rtl;