Verilog 编程实验(4)-7位译码器的设计与实现

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数码管7位译码器的真值表：

Implementation part:

module Seven_Decoder_B(data_in,data_out,EN);input [3:0] data_in ;input EN ;output [6:0] data_out ;reg [6:0] data_out ;always @(data_in or EN )begindata_out = 7'b1111111;if (EN == 1)case (data_in )4'b0000: data_out = 7'b1000000; // 04'b0001: data_out = 7'b1111001; // 14'b0010: data_out = 7'b0100100; // 24'b0011: data_out = 7'b0110000; // 34'b0100: data_out = 7'b0011001; // 44'b0101: data_out = 7'b0010010; // 54'b0110: data_out = 7'b0000011; // 64'b0111: data_out = 7'b1111000; // 74'b1000: data_out = 7'b0000000; // 84'b1001: data_out = 7'b0011000; // 94'b1010: data_out = 7'b0001000; // A4'b1011: data_out = 7'b0000011; // b4'b1100: data_out = 7'b0100111; // c4'b1101: data_out = 7'b0100001; // d4'b1110: data_out = 7'b0000110; // E4'b1111: data_out = 7'b0001110; // Fdefault: data_out = 7'b1111111;endcaseendendmodule

Simulation part:

module Seven_Decoder_B_Test2;    // Inputs    reg [3:0] data_in;    reg EN;    // Outputs    wire [6:0] data_out;    // Instantiate the Unit Under Test (UUT)    Seven_Decoder_B uut (        .data_in(data_in),         .data_out(data_out),         .EN(EN)    );    initial begin        // Initialize Inputs        data_in = 0;        EN = 1;        // Wait 100 ns for global reset to finish        #100;        // Add stimulus here        data_in= 4'b0000;        #100;        data_in = 4'b0001;        #100;        data_in = 4'b0010;        #100;        data_in = 4'b0011;        #100;        data_in = 4'b0100;        #100;        data_in = 4'b0101;        #100;        data_in = 4'b0110;        #100;        data_in = 4'b0111;        #100        data_in = 4'b1000;        #100;        data_in = 4'b1001;        #100;        data_in = 4'b1010;        #100;        data_in = 4'b1011;        #100;        data_in = 4'b1100;        #100;        data_in = 4'b1101;        #100;        data_in = 4'b1110;        #100;        data_in = 4'b1111;        #100;        endendmodule

RTL Schematic:

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