Verilog VGA 动态屏保——弹射

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在上一篇博文 Verilog VGA 静态显示图片
的基础上使图片可以向左上、左下、右上、右下自动移动，且遇边界反弹，即类似动态屏保的效果。

Verilog代码

module vgaRGB(input wire [9:0]hc, vc, input wire videoen, mclk, rst,       output reg [2:0] r, g, output reg [1:0] b    );//up、down、left、right规定图片显示范围reg [9:0] up = 10'd99, down = 10'd300, left = 10'd204, right = 10'd405;//updown为1表示向下移动，为0表示向上移动，leright为1表示向左移动，为0表示向右移动reg updown = 1, leright = 1;reg [19:0] count = 0;always @ (posedge mclk)begin        if(rst)            count <= 0;         else           count <= count + 1'b1;        //控制方块移动速度，肉眼可见即可        if(count == 20'b11111111111111111111)           begin             if(updown == 0) //向上                  begin                    up = up - 1'b1;                     down = down - 1'b1;                   end                else  //向下                  begin                      up = up + 1'b1;                      down = down + 1'b1;                  end                if(leright == 0)  //向左                  begin                     left = left - 1'b1;                      right = right - 1'b1;                   end                else  //向右                  begin                      left = left + 1'b1;                      right = right + 1'b1;                  end                //接触边界反弹                    if(up == 32 || down == 510)                   updown = ~updown;               if(left == 145 || right == 783)                  leright = ~leright;            end     end//ip核reg [15:0] addr = 0;wire [7:0] data;ip ROM0( .clka(mclk), .addra(addr), .douta(data) );always @ (posedge mclk)begin      if(videoen == 1)          begin            if(vc < down && vc > up && hc < right && hc > left)                            begin                addr <= (vc - up - 1) * 200 + (hc - left) - 1;               r <= data[7:5];               g <= data[4:2];               b <= data[1:0];              end             else               begin                 r <= 3'b111;                 g <= 3'b111;                 b <= 2'b11;                end          end     else       begin         r <= 3'b0;           g <= 3'b0;           b <= 2'b0;        endendendmodule

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