ARMv8-A系列学习笔记(5)--Chapter 15 Power Management

ARM Cortex-A Series Programmer’s Guide for ARMv8-A

Chapter 15 Power Management

两类功耗：

静态：即漏电流，与SILICON面积成正比，制成、工艺（fabrication geometries）越小，静态功耗占比越高

动态：由于晶体管开关，与时钟速率正相关，与晶体管数量正相关

软件根据计算量，动态调整CORES的电源状态，有两个方面：

1. IDLE MANAGEMENT

2. DYNAMIC VOLTAGE AND FREQUENCY SCALING

WAKEUP LATENCY：time required to move from a low-power state to a running state

CLOCK-GATING：  STOP THE CLOCK OF THE CORE (DYNAMIC ONLY)

POWER-GATING:    REMOVE POWER (DYNAMIC & STATIC)

LOW-POWER STATEs: 由 clock-gated, power-gated的components的数量与程度来分类

IDLE.STANDBY:

core is left powered-up

clocks are stopped -- clock-gated, static/leakage only,  clocking for small amount of logic that looks out for the wake-up condition

entered: WFI, WFE

wakeup condition: interrupt, event, SEV instruction, request from SCU for a cache coherency operation in a multi-core system 

wakeup latency: two-clock-cycles (negligible effect on latency and responsiveness of the core)

IDLE.RETENTION

OS层面，与STANDBY没有差异

在ENTRY METHOD, LATENCY, USE-RELATED CONSTRAINTS等方面存在差异

在EXTERNAL DEBUG方面与STANDBY存在差异

IDLE.POWER DOWN

core is powered off  -- 断电

core state is saved and restored -- 保存与恢复

need core reset when power level been restored -- 需要RESET

IDLE.DORMANT MODE

core logic is powered down -- 断电

cache RAMs are left powered up (live data and code persists i the caches) -- 环境存在cache中

in a multi-core system, such core must isolate themselves from the coherence domain -- 处于该状态下的core， 将不纳入coherence的domain

IDLE.Hotplug

动态开关core

与power-down的差异：

1. hot unplugged状态下，软件停用所有与该CORE相关的中断与线程， 对OS来讲，相当于该CORE不存在 

2. OS需要使用显式的指令，将该CORE转换到HOT PLUG状态， 在该显式指令之后，才开始在该CORE上调度线程，全能中断

DVFS: dynamic voltage and frequency scaling

1.与工作频率成线性关系

2.与工作电压成平方关系

P = C *  V*V  * f

调整core clock的工作频率

频率下降，也使电压下降

电压下降，则同时降低动态与静态功耗

OPP: OPERATING PERFORMANCE POINT, system DVFS curve

OS PROVIDES DVFS POLICIES