ARMv8-A系列学习笔记(7)--Chapter 13 Memory Ordering
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Chapter 13
两种NORMAL与DEVICE (ARMV7 还有一种STRONGLY ORDERED,V8没有了)
NORMAL:
all code, most data regions
RAM, Flash, or ROM
weakly ordered, fewer restrictions placed on the processor
can re-order, repeat, and merge accesses to Normal memory
be access speculatively (without being explicitly referenced in the program)
被标为NORMAL的MEMORY, 可以显式使用BARRIER来实现ORDERING
DEVICE:
只有NON-CACHEABLE, OUTER-SHAREABLE
access have a side-effect
only used for peripherals in system
no speculative (exception NEON)
有以下几种属性:
Gathering
Re-ordering
Early Write Acknowledgement (write buffer between core and device memory)
所谓的
Non-shareable
Inner shareable
Outer shareable
Full system
Memory Ordering
两种NORMAL与DEVICE (ARMV7 还有一种STRONGLY ORDERED,V8没有了)
NORMAL:
all code, most data regions
RAM, Flash, or ROM
weakly ordered, fewer restrictions placed on the processor
can re-order, repeat, and merge accesses to Normal memory
be access speculatively (without being explicitly referenced in the program)
被标为NORMAL的MEMORY, 可以显式使用BARRIER来实现ORDERING
DEVICE:
只有NON-CACHEABLE, OUTER-SHAREABLE
access have a side-effect
only used for peripherals in system
no speculative (exception NEON)
有以下几种属性:
Gathering
Re-ordering
Early Write Acknowledgement (write buffer between core and device memory)
所谓的
Non-shareable
Inner shareable
Outer shareable
Full system
是否可以理解为,对同一块内存区域,多个观察者,之间的范围分类
Barriers/Fence:
MASTER <--> INTERCONNECT <--> SLAVE DEVICE
只有MASTER可以观察(OBSERVE)TRANSFERS
只有MASTER发起事务(TRANSACTIONS)
MASTER发起事务的顺序,与事务被(SLAVE DEVICE)完成的顺序,不一定相同,因为,有可能在INTERCONNECT中,被RE-ORDERED了
OBSERVABILITY:
I have observed your write when I can read what you wrote and I have observed your read when I can no longer change the value you read
写的可以被读到
读的不再被改变
ISB: ISB is required to ensure that the effects of those operations are seen by the instructions that follow
DMB
DSB: DSB is required to ensure that the maintenance operations complete
不是很明白:ONE-WAY BARRIERS
LOAD-ACQUIRE, STORE-RELEASE
0 0
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