并转串模块设计

顶层框架设计：

并转串代码：

module para_serial(clk, rst_n,sda ,en);input clk ;input rst_n ;output reg sda ;output reg en ;reg [7:0] sda_buf ;reg [3:0] counter ;always @ (posedge clk or negedge rst_n)    begin   if (!rst_n)     begin     sda <= 0;  sda_buf <= 8'b1001_1101 ;  counter <= 0 ;  en <= 0 ;  end      else     begin   if(counter < 8 )      begin     en <= 1 ;  counter <= counter + 1'b1 ;  sda_buf <= {sda_buf[6:0],sda_buf[7]};  sda <= sda_buf[7];   end  else    begin       counter <= 0 ; sda <= 0; en <= 0;      end end    end endmodule 

测试代码：

`timescale 1ns/1psmodule para_serial_tb;reg clk ;reg rst_n ;wire sda ;wire en ;initial    begin    clk = 0 ; rst_n = 0; # 100.1 rst_n = 1 ;  end always #10 clk =~clk ;para_serial para_serial_dut(.clk(clk), .rst_n(rst_n),.sda(sda) ,.en(en)); endmodule

仿真验证：