verilog入门知识【2】

多输入逻辑门：

module Doors(input wire a,input wire b,output wire [5:0] z    );    assign z[5]=a&b;    assign z[4]=~(a&b);    assign z[3]=a|b;    assign z[2]=~(a|b);    assign z[1]=a^b;    assign z[0]=a~^b;endmodule

仿真：

module sim();reg a;reg b;wire [5:0]z;Doors u1(a,b,z);initial begina=0;b=0;endalways begin#10 a=~a;#40 b=~b;endendmodule