DDS

DDS（Direct Digital Systhesize 直接数字频率合成器）具有相对带宽很宽、频率捷变速率快、频率分辨率高、输出相位连续、可输出带宽的正交信号、可编程、全数字化和便于集成的优越性。

DDS的理论是根据奈奎斯特采样定理，对于一个周期连续信号，可以沿其相位轴方向，以等量的相位间隔对其进行相位或幅度的采样，得到周期信号的离散相位幅度序列，并对模拟幅度值进行量化，量化后的幅值采用相应的二进制编码。将编固化到ROM中，每个存储单元的地址就是相位采样的地址，存储单元的内容就是周期信号的幅值。

代码：

module dds_module(inputclk_50m,inputrst_n,input [31:0]pid_frequency,input [31:0]pid_phase,input [2:0]pid_type,inputpic_ce,inputpic_we,output [7:0]pod_dds);reg [31:0]add_a,n_add_a;reg [31:0]add_b,n_add_b;reg [31:0]add_c,n_add_c;wire [31:0]add;wire [9:0]addr;wire [7:0]Sawtooth_data;wire [7:0]Sine_data;wire [7:0]Square_data;wire [7:0]Triangular_data;always @ (posedge clk_50m)beginif (!rst_n)add_a <= 32'd0;elseadd_a <= n_add_a;endalways @ (*)beginif (pic_we)n_add_a = pid_frequency;elsen_add_a = 32'd0;endalways @ (posedge clk_50m)beginif (!rst_n)add_b <= 32'd0;elseadd_b <= n_add_b;endalways @ (*)beginif (pic_ce)n_add_b = pid_phase;elsen_add_b = 32'd0;endalways @ (posedge clk_50m)beginif (!rst_n)add_c <= 32'd0;elseadd_c <= n_add_c;endalways @ (*)beginif (pic_ce)n_add_c = add_c + add_a;elsen_add_c = 32'd0;endassign add = add_c + add_b;assign addr = add[31:22];assign pod_dds = (pid_type[2] == 1'b0) ? 8'd0 : ((pid_type[1]) ? ((pid_type[0]) ? Sawtooth_data : Sine_data) : ((pid_type[0]) ? Square_data : Triangular_data));rom_Sawtoothrom_Sawtooth_inst (.address ( addr ),.clock ( clk_50m ),.q ( Sawtooth_data ));rom_Sinerom_Sine_inst  (.address ( addr ),.clock ( clk_50m ),.q ( Sine_data ));rom_Squarerom_Square_inst (.address ( addr ),.clock ( clk_50m ),.q ( Square_data ));rom_Triangularrom_Triangular_inst (.address ( addr ),.clock( clk_50m ),.q ( Triangular_data ));endmodule