Vivado DDS

1.Matlab生成coe文件

 t=0:2*pi/2^12:2*pi y=0.5*sin(t)+0.5; r=ceil(y*(2^8-1)); %将小数转换为整数，ceil是向上取整。 fid = fopen('sin.coe','w'); %写到sin.coe文件，用来初始化sin_rom

2.DDS原理

F1=F0∗K/2N

F0是CLK频率，F1是DDS产生的信号频率。

3.verilog代码如下

`timescale 1ns / 1psmodule nco(            input mclk,            input rst_n,            input [31:0]fword,//frequency control            input [11:0]pword,//phase control            output [9:0]da_data    );    reg [31:0]r_fword=32'd0;    reg [11:0]r_pword=12'd0;    reg [31:0]fcnt=32'd0;    wire [11:0]addr_rom;    //同步寄存器    always @(posedge mclk)    begin            r_fword <= fword;            r_pword <= pword;        end    always @(posedge mclk or posedge rst_n)    begin        if(!rst_n)            fcnt <= 32'd0;        else            fcnt <= fcnt + r_fword;        end   // 取高11位相当于除以4096    assign addr_rom = fcnt[31:20] + r_pword;    //custom sin_rom    blk_mem_gen_0 sin_rom (    .clka(mclk),    // input wire clka    .addra(addr_rom),  // input wire [11 : 0] addra    .douta(da_data)  // output wire [9 : 0] douta    );endmodule

4.Simulation

`timescale 1ns / 1psmodule nco(            input mclk,            input rst_n,            input [31:0]fword,//frequency control            input [11:0]pword,//phase control            output [9:0]da_data    );    reg [31:0]r_fword=32'd0;    reg [11:0]r_pword=12'd0;    reg [31:0]fcnt=32'd0;    wire [11:0]addr_rom;    //同步寄存器    always @(posedge mclk)    begin            r_fword <= fword;            r_pword <= pword;        end    always @(posedge mclk or posedge rst_n)    begin        if(!rst_n)            fcnt <= 32'd0;        else            fcnt <= fcnt + r_fword;        end   // 取高11位相当于除以4096    assign addr_rom = fcnt[31:20] + r_pword;    //custom sin_rom    blk_mem_gen_0 sin_rom (    .clka(mclk),    // input wire clka    .addra(addr_rom),  // input wire [11 : 0] addra    .douta(da_data)  // output wire [9 : 0] douta    );endmodule