Verilog HDL 音乐盒设计
来源:互联网 发布:qt 5编程入门 pdf 编辑:程序博客网 时间:2024/05/17 03:23
module music(clk,beep,pause,stop,switch,led); //定义时钟及几个功能变量
input clk,pause,switch,stop; //输入变量
output beep; //输出变量,即蜂鸣器发声
output[8:1]led;
reg[8:1]led;
reg beep_r; //定义几个中间变量
reg a;
reg b;
reg c;
reg[7:0]state;
reg[7:0]state1;
reg[7:0]state2;
reg[15:0]count,count_end;
reg[23:0]count1;
parameter L_5=16'd61224,
L_6=16'd54545,
M_1=16'd45863,
M_2=16'd40864,
M_3=16'd36402,
M_5=16'd30612,
M_6=16'd27273,
H_1=16'd22956;
parameter TIME=12000000; //时钟频率
assign beep=beep_r;
always@(posedge pause)
begin
a=!a; //暂停
end
always@(posedge stop)
begin
b=!b; //停止
end
always@(posedge switch)
begin
c=!c; //切换
end
always@(posedge clk)
begin
if(a==1||b==1)
beep_r=1'b0;
else
count<=count+1'b1;
if(count==count_end)
begin
count<=16'h0;
beep<=!beep_r;
end
end
always@(posedge clk)
begin
if(count1<TIME )
count=count1+1'b1;
else
begin
count1=24'd0;
if(state1==8'd147||state2==8'd60)
state=8'd0;
if(a==1&b==0)
begin
state=state;
end
if(a==0&b==0)
state=state+1'b1;
if(a==0&b==1)
begin
state=8'd0;
end
if(a==1&b==1)
state=state+1'b1;
if(c==1) //曲目1
begin
state1=state;
case(state1)
8'd0,8'd1: count_end=L_5;
8'd2,8'd3,8'd4,8'd5,8'd6,8'd7,8'd8: count_end=M_1;
8'd9,8'd10: count_end=M_3;
8'd11,8'd12,8'd13,8'd14: count_end=M_2;
8'd15: count_end=M_1;
8'd16,8'd17: count_end=M_2;
8'd18,8'd19: count_end=M_3;
8'd20,8'd21,8'd22,8'd23,8'd24: count_end=M_1;
8'd25,8'd26: count_end=M_3;
8'd27,8'd28: count_end=M_5;
8'd29,8'd30,8'd31,8'd32,8'd33: count_end=M_6;
8'd34,8'd35,8'd36,8'd37,8'd38: count_end=M_6;
8'd39,8'd40,8'd41,8'd42: count_end=M_5;
8'd43,8'd44,8'd45: count_end=M_3;
8'd46,8'd47: count_end=M_1;
8'd48,8'd49,8'd50,8'd51: count_end=M_2;
8'd52: count_end=M_1;
8'd53,8'd54: count_end=M_2;
8'd55,8'd56: count_end=M_3;
8'd57,8'd58,8'd59,8'd60: count_end=M_1;
8'd61,8'd62,8'd63: count_end=L_6;
8'd64,8'd65: count_end=M_5;
8'd66,8'd67,8'd68,8'd69: count_end=M_1;
8'd70,8'd71,8'd72,8'd73: count_end=M_1;
8'd74,8'd75: count_end=M_6;
8'd76,8'd77,8'd78,8'd79: count_end=M_5;
8'd80,8'd81,8'd82: count_end=M_3;
8'd83,8'd84: count_end=M_1;
8'd85,8'd86,8'd87,8'd88: count_end=M_2;
8'd89: count_end=M_1;
8'd90,8'd91: count_end=M_2;
8'd92,8'd93: count_end=M_6;
8'd94,8'd95,8'd96,8'd97: count_end=M_5;
8'd98,8'd99,8'd100: count_end=M_3;
8'd101,8'd102: count_end=M_5;
8'd103,8'd104,8'd105,8'd106: count_end=M_6;
8'd107,8'd108,8'd109,8'd110: count_end=M_6;
8'd111,8'd112: count_end=H_1;
8'd113,8'd114,8'd115,8'd116: count_end=M_5;
8'd117,8'd118,8'd119: count_end=M_3;
8'd120,8'd121: count_end=M_1;
8'd122,8'd123,8'd124,8'd125: count_end=M_2;
8'd126: count_end=M_1;
8'd127,8'd128: count_end=M_2;
8'd129,8'd130: count_end=M_3;
8'd131,8'd132,8'd133,8'd134: count_end=M_1;
8'd135,8'd136,8'd137: count_end=L_6;
8'd138,8'd139: count_end=M_5;
8'd140,8'd141,8'd142,8'd143: count_end=M_1;
8'd144,8'd145,8'd146,8'd147: count_end=M_1;
default:count_end=16'hffff;
endcase
end
if(c==0) //曲目2
begin
state2=state;
case(state)
8'd0,8'd1,8'd2: count_end=M_6;
8'd3: count_end=M_5;
8'd4,8'd5: count_end=M_3;
8'd6,8'd7,8'd8: count_end=M_5;
8'd9: count_end=H_1;
8'd10: count_end=M_6;
8'd11: count_end=M_5;
8'd12,8'd13,8'd14,8'd15: count_end=M_6;
8'd16,8'd17: count_end=M_3;
8'd18: count_end=M_5;
8'd19: count_end=M_6;
8'd20,8'd21: count_end=M_5;
8'd22: count_end=M_3;
8'd23: count_end=M_2;
8'd24: count_end=M_1;
8'd25: count_end=L_6;
8'd26: count_end=M_5;
8'd27: count_end=M_3;
8'd28,8'd29,8'd30,8'd31,8'd32,8'd33,8'd34:count_end=M_2;
8'd35: count_end=M_3;
8'd36,8'd37,8'd38: count_end=M_5;
8'd39: count_end=M_6;
8'd40,8'd41,8'd42: count_end=M_3;
8'd43,8'd44: count_end=M_2;
8'd45,8'd46,8'd47,8'd48: count_end=M_1;
8'd49,8'd50,8'd51: count_end=M_5;
8'd52: count_end=M_3;
8'd53: count_end=M_2;
8'd54: count_end=M_1;
8'd55: count_end=L_6;
8'd56: count_end=M_1;
8'd57,8'd58,8'd59,8'd60: count_end=L_5;
default:count_end=16'hffff;
endcase
end
end
end
always @(count)
begin
case(count)
L_5:led=8'b1111_1111;
L_6:led=8'b0111_1111;
M_1:led=8'b0011_1111;
M_2:led=8'b0001_1111;
M_3:led=8'b0000_1111;
M_5:led=8'b0000_0111;
M_6:led=8'b0000_0011;
H_1:led=8'b0000_0000;
default : led=8'b0;
endcase
end
endmodule
input clk,pause,switch,stop; //输入变量
output beep; //输出变量,即蜂鸣器发声
output[8:1]led;
reg[8:1]led;
reg beep_r; //定义几个中间变量
reg a;
reg b;
reg c;
reg[7:0]state;
reg[7:0]state1;
reg[7:0]state2;
reg[15:0]count,count_end;
reg[23:0]count1;
parameter L_5=16'd61224,
L_6=16'd54545,
M_1=16'd45863,
M_2=16'd40864,
M_3=16'd36402,
M_5=16'd30612,
M_6=16'd27273,
H_1=16'd22956;
parameter TIME=12000000; //时钟频率
assign beep=beep_r;
always@(posedge pause)
begin
a=!a; //暂停
end
always@(posedge stop)
begin
b=!b; //停止
end
always@(posedge switch)
begin
c=!c; //切换
end
always@(posedge clk)
begin
if(a==1||b==1)
beep_r=1'b0;
else
count<=count+1'b1;
if(count==count_end)
begin
count<=16'h0;
beep<=!beep_r;
end
end
always@(posedge clk)
begin
if(count1<TIME )
count=count1+1'b1;
else
begin
count1=24'd0;
if(state1==8'd147||state2==8'd60)
state=8'd0;
if(a==1&b==0)
begin
state=state;
end
if(a==0&b==0)
state=state+1'b1;
if(a==0&b==1)
begin
state=8'd0;
end
if(a==1&b==1)
state=state+1'b1;
if(c==1) //曲目1
begin
state1=state;
case(state1)
8'd0,8'd1: count_end=L_5;
8'd2,8'd3,8'd4,8'd5,8'd6,8'd7,8'd8: count_end=M_1;
8'd9,8'd10: count_end=M_3;
8'd11,8'd12,8'd13,8'd14: count_end=M_2;
8'd15: count_end=M_1;
8'd16,8'd17: count_end=M_2;
8'd18,8'd19: count_end=M_3;
8'd20,8'd21,8'd22,8'd23,8'd24: count_end=M_1;
8'd25,8'd26: count_end=M_3;
8'd27,8'd28: count_end=M_5;
8'd29,8'd30,8'd31,8'd32,8'd33: count_end=M_6;
8'd34,8'd35,8'd36,8'd37,8'd38: count_end=M_6;
8'd39,8'd40,8'd41,8'd42: count_end=M_5;
8'd43,8'd44,8'd45: count_end=M_3;
8'd46,8'd47: count_end=M_1;
8'd48,8'd49,8'd50,8'd51: count_end=M_2;
8'd52: count_end=M_1;
8'd53,8'd54: count_end=M_2;
8'd55,8'd56: count_end=M_3;
8'd57,8'd58,8'd59,8'd60: count_end=M_1;
8'd61,8'd62,8'd63: count_end=L_6;
8'd64,8'd65: count_end=M_5;
8'd66,8'd67,8'd68,8'd69: count_end=M_1;
8'd70,8'd71,8'd72,8'd73: count_end=M_1;
8'd74,8'd75: count_end=M_6;
8'd76,8'd77,8'd78,8'd79: count_end=M_5;
8'd80,8'd81,8'd82: count_end=M_3;
8'd83,8'd84: count_end=M_1;
8'd85,8'd86,8'd87,8'd88: count_end=M_2;
8'd89: count_end=M_1;
8'd90,8'd91: count_end=M_2;
8'd92,8'd93: count_end=M_6;
8'd94,8'd95,8'd96,8'd97: count_end=M_5;
8'd98,8'd99,8'd100: count_end=M_3;
8'd101,8'd102: count_end=M_5;
8'd103,8'd104,8'd105,8'd106: count_end=M_6;
8'd107,8'd108,8'd109,8'd110: count_end=M_6;
8'd111,8'd112: count_end=H_1;
8'd113,8'd114,8'd115,8'd116: count_end=M_5;
8'd117,8'd118,8'd119: count_end=M_3;
8'd120,8'd121: count_end=M_1;
8'd122,8'd123,8'd124,8'd125: count_end=M_2;
8'd126: count_end=M_1;
8'd127,8'd128: count_end=M_2;
8'd129,8'd130: count_end=M_3;
8'd131,8'd132,8'd133,8'd134: count_end=M_1;
8'd135,8'd136,8'd137: count_end=L_6;
8'd138,8'd139: count_end=M_5;
8'd140,8'd141,8'd142,8'd143: count_end=M_1;
8'd144,8'd145,8'd146,8'd147: count_end=M_1;
default:count_end=16'hffff;
endcase
end
if(c==0) //曲目2
begin
state2=state;
case(state)
8'd0,8'd1,8'd2: count_end=M_6;
8'd3: count_end=M_5;
8'd4,8'd5: count_end=M_3;
8'd6,8'd7,8'd8: count_end=M_5;
8'd9: count_end=H_1;
8'd10: count_end=M_6;
8'd11: count_end=M_5;
8'd12,8'd13,8'd14,8'd15: count_end=M_6;
8'd16,8'd17: count_end=M_3;
8'd18: count_end=M_5;
8'd19: count_end=M_6;
8'd20,8'd21: count_end=M_5;
8'd22: count_end=M_3;
8'd23: count_end=M_2;
8'd24: count_end=M_1;
8'd25: count_end=L_6;
8'd26: count_end=M_5;
8'd27: count_end=M_3;
8'd28,8'd29,8'd30,8'd31,8'd32,8'd33,8'd34:count_end=M_2;
8'd35: count_end=M_3;
8'd36,8'd37,8'd38: count_end=M_5;
8'd39: count_end=M_6;
8'd40,8'd41,8'd42: count_end=M_3;
8'd43,8'd44: count_end=M_2;
8'd45,8'd46,8'd47,8'd48: count_end=M_1;
8'd49,8'd50,8'd51: count_end=M_5;
8'd52: count_end=M_3;
8'd53: count_end=M_2;
8'd54: count_end=M_1;
8'd55: count_end=L_6;
8'd56: count_end=M_1;
8'd57,8'd58,8'd59,8'd60: count_end=L_5;
default:count_end=16'hffff;
endcase
end
end
end
always @(count)
begin
case(count)
L_5:led=8'b1111_1111;
L_6:led=8'b0111_1111;
M_1:led=8'b0011_1111;
M_2:led=8'b0001_1111;
M_3:led=8'b0000_1111;
M_5:led=8'b0000_0111;
M_6:led=8'b0000_0011;
H_1:led=8'b0000_0000;
default : led=8'b0;
endcase
end
endmodule
0 0
- Verilog HDL 音乐盒设计
- Verilog HDL模块化设计
- Verilog HDL 与数字电路设计
- 设计与验证:verilog hdl
- Verilog HDL 有限状态机的设计
- [verilog读书笔记]1.Verilog HDL数字设计
- Verilog HDL DDS设计(作业3)
- Verilog HDL 典型组合逻辑电路设计
- 基于Verilog HDL语言的32X8 FIFO设计
- 【学习笔记】【第一章】【Verilog HDL数字集成电路设计方法概述】
- 数字电路设计之同步状态机的verilog HDL实现
- Verilog HDL数字设计与综合 笔记(1)
- Verilog HDL数字设计与综合 笔记(2)
- NYOJ91 阶乘之和 与全加器设计Verilog HDL
- 基于Verilog HDL的模60BCD码计数器设计
- Verilog HDL简明教程
- Verilog HDL简介
- Verilog HDL简明教程
- 一个document.documentElement.clientWidth为0的问题
- (VS2010刚装上就不能编译)LINK : fatal error LNK1123: 转换到 COFF 期间失败: 文件无效或损坏
- linux下挂载移动硬盘和U盘的方法
- 超级change
- 几个硬盘速度对比
- Verilog HDL 音乐盒设计
- TNS-01190: 用户无权执行所请求的监听程序命令"问题解决
- 无法打开包括文件:“afxcontrolbars.h”: No such file or directory
- 教你透彻了解红黑树
- LJ-V7000 Series Communication Library
- Log4J学习【八】Log4J对3个组件的使用
- 增强的blockrecover
- 由类的private成员引发的思考
- js中删除table里所有行(转)