msp40 PLL

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//******************************************************************************
//  MSP430F552x Demo - Timer_B, Toggle P1.0, CCR0 Up Mode ISR, DCO SMCLK
//
//  Description: Toggle P1.0 using software and TB_0 ISR. Timer_B is
//  configured for up mode, thus the timer overflows when TBR counts
//  to CCR0. In this example, CCR0 is loaded with 50000.
//  ACLK = n/a, MCLK = SMCLK = TBCLK = default DCO ~1.045MHz
//
//           MSP430F552x
//         ---------------
//     /|\|               |
//      | |               |
//      --|RST            |
//        |               |
//        |           P1.0|-->LED
//
//   Bhargavi Nisarga
//   Texas Instruments Inc.
//   April 2009
//   Built with CCSv4 and IAR Embedded Workbench Version: 4.21
//******************************************************************************
#include <msp430f5529.h>
#define TRUE 1
#define FALSE 0

unsigned int ramp_up = FALSE;
unsigned int ramp_cycle=0;
unsigned int last_TA1CCR=0;
unsigned int lock_value;

int main(void)
{
  WDTCTL = WDTPW + WDTHOLD;                 // Stop WDT
  P1DIR |= BIT0+BIT1;                            // Set P1.0 to output direction
  TBCCTL0 = CCIE;                           // TBCCR0 interrupt enabled
  TBCCR0 = 50000;
  TBCTL = TBSSEL_2 + MC_1 + TBCLR;          // SMCLK, upmode, clear TBR
 
  P2DIR |= BIT1+BIT3;                       //
  P2SEL |= BIT0+BIT1+BIT3;                  // P2.0 TA1.1 CAP
                                            // P2.1 TA1.2 COMPARE OUT
                                            // P2.3 TA2.0 COMPARE OUT
 
  P4DIR |= BIT0;                            // PWM Output
  P1DIR |= BIT0;                            // indicator

 
  TA1CTL = TASSEL__SMCLK + MC__CONTINOUS+TACLR; 
  TA1CCTL1 = CM_3+SCS+CAP+CCIS_0+CCIE;      // Capture Both Edges from TA1.1, Enable Interrupt 
  TA1CCTL2 = OUTMOD_4;                      // toggle
 
  TA2CTL = TASSEL__SMCLK + MC__CONTINOUS+TACLR; 
  TA2CCTL0 = OUTMOD_4+CCIE;                 // toggle, CCR0 interrupt enabled
  lock_value=1000;
  TA2CCR0 += lock_value;
 
 
  while(1)
  {
  __bis_SR_register(LPM0_bits + GIE);       // Enter LPM0, enable interrupts
//  __no_operation();   

  if((ramp_up==FALSE)&&(TBCCR0>10000))
  {
  TBCCR0-=50;       
                     // For debugger
  }
  else
    if(TBCCR0<50000) TBCCR0+=50;
 
  if(TBCCR0<=10000) ramp_up=TRUE;
  if(TBCCR0>=50000) ramp_up=FALSE;
  } 
}

// Timer B0 interrupt service routine
#pragma vector=TIMERB0_VECTOR
__interrupt void TIMERB0_ISR (void)
{
  P4OUT ^= BIT0;                            // Toggle P1.0 using exclusive-OR
  __bic_SR_register_on_exit(LPM0_bits);
}

 

// Timer1 interrupt service routine
#pragma vector=TIMER2_A0_VECTOR
__interrupt void TIMER2_A0_ISR(void)
{
  TA2CCR0 += lock_value;                         // Add Offset to CCR0
}

#pragma vector=TIMER1_A1_VECTOR
__interrupt void Timer_A1(void)
{
  unsigned int temp;
  switch( TA1IV )
  {
   case  2:
          temp=TA1CCR1;
          TA1CCR2=temp+((temp-last_TA1CCR)>>1);         //offest = period/2
          lock_value=(temp-last_TA1CCR)>>3;             //8x the frequency
          last_TA1CCR=temp;

         
          P1OUT ^= BIT0;
          break;                           
   case  4: break;                          // CCR2 not used
   case  6: break;                          // CCR3 not used
   case  8: break;                          // CCR4 not used
   case 10: break;                          // CCR5 not used
   case 12: break;                          // Reserved not used
   case 14:                                 // Overflow
          __no_operation();   
          //while(1);                         // If input frequency < 200Hz, trap here
   default: break;
  } 
}