u-boot-2014.10移植第14天----在SDRAM中运行

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硬件平台：tq2440
开发环境：Ubuntu-3.11
u-boot版本：2014.10
本文允许转载，请注明出处：http://blog.csdn.net/fulinus

昨天遇到编译错误，我们从错误提示中寻找解决方法：

信息1：CHK include/config.h

/* Automatically generated - do not edit */#define CONFIG_BOARDDIR board/samsung/tq2440#include <config_defaults.h>#include <configs/tq2440.h>#include <asm/config.h>#include <config_fallbacks.h>#include <config_uncmd_spl.h>

注释中说这个文件是自动生成的，没有编辑。

信息2：cc1: error: bad value (armv4) for -march= switch

这个问题网上说是没有指定交叉编译器(http://bbs.csdn.net/topics/390769229),添加交叉编译器：

# set default to nothing for native buildsifeq ($(HOSTARCH),$(ARCH))CROSS_COMPILE ?=endif#add by fulinuxCROSS_COMPILE=arm-linux-

再次make命令确实是编译成功了。生成u-boot.bin执行，文件但是该文件是基于smdk2410平台的,我们还没有对代码进行修改，故还不能在tq2440平台上运行。下面对源码进行修改。

u-boot-2014.10]$ make distclean

该命令可以清除我们前面编译的结果，恢复到最初的状态。下次编译时不要忘了make menuconfig重新配置文件。

这里我们借鉴彭东林朋友移植u-boot-2014.04的经验来修改我们的代码：

修改tq2440.h

我们首先修改tq2440.h头文件，硬件的信息基本都是在这里配置的。

注：下面代码前加“-”符号的表示删除，加“+”符号的表示添加

特别指明是三星的s3c2440芯片：

- #define CONFIG_S3C2410+ #define CONFIG_S3C2440

指定开发板类型：

- #define CONFIG_SMDK2410+ #define CONFIG_TQ2440

修改命令提示符：

- #define CONFIG_SYS_PROMPT   "SMDK2410 # "+ #define CONFIG_SYS_PROMPT   "TQ2440 # "

屏蔽不需要的硬件支持，以及暂时不用支持的功能：

因为没有cs8900网卡，只有DM9000网卡，暂时不考虑网络功能：

+ #define NONE_FLAG 0+ #if NONE_FLAG  #define CONFIG_CS8900       /* we have a CS8900 on-board */#define CONFIG_CS8900_BASE  0x19000300#define CONFIG_CS8900_BUS16 /* the Linux driver does accesses as shorts */+ #endif

屏蔽USB功能：

+ #if NONE_FLAG#define CONFIG_USB_OHCI#define CONFIG_USB_OHCI_S3C24XX#define CONFIG_USB_KEYBOARD#define CONFIG_USB_STORAGE#define CONFIG_DOS_PARTITION+ #endif

屏蔽一些命令：

+ + #if NONE_FLAG#define CONFIG_CMD_DHCP#define CONFIG_CMD_ELF#define CONFIG_CMD_NAND#define CONFIG_CMD_PING#define CONFIG_CMD_REGINFO#define CONFIG_CMD_USB+ #endif+

屏蔽文件系统操作命令：

#if NONE_FLAG#define CONFIG_CMD_FAT#define CONFIG_CMD_EXT2#define CONFIG_CMD_UBI#define CONFIG_CMD_UBIFS#define CONFIG_CMD_MTDPARTS#define CONFIG_MTD_DEVICE#define CONFIG_MTD_PARTITIONS#define CONFIG_YAFFS2#define CONFIG_RBTREE#endif

start.S文件

前面分析启动流程时指出，起始位置是从arch/arm/lib/vectors.S开始的，再跳转到arch/arm/cpu/arm920t/start.S，修改start.S文件：

屏蔽子中断：

# if defined(CONFIG_S3C2410)ldr r1, =0x3ffldr r0, =INTSUBMSKstr r1, [r0]+ # elif defined(CONFIG_S3C2440)+ ldr r1, =0x7fff+ ldr r0, =INTSUBMSK+ str r1, [r0]# endif

设置时钟：

# if defined(CONFIG_S3C2440) /* 到#else前的内容都是新添加的 */# define MPLLCON 0x4C000004 /* 系统主频配置寄存器 */# define UPLLCON 0x4C000008 /* USB频率配置寄存器 */# define CAMDIVN 0x4C000018 /* CAMERA时钟分频寄存器 */# define MMDIV_405 (0x7f<<12)# define MPSDIV_405 0x21# define UMDIV_48 (0x38<<12)# define UPSDIV_48 0X22    ldr r0, =CAMDIVN    mov r1, #0        str r1, [r0]                        /* FCLK:HCLK:PCLK = 1:2:4 */    /* default FCLK is 120 MHz ! */    ldr r0, =CLKDIVN    mov r1, #0x05     str r1, [r0]                        /* 如果HDIVN不等于0，CPU必须设置为异步总线模式 */    mrc p15, 0, r0, c1, c0, 0    orr r0, r0, #0xC0000000    mcr p15, 0, r0, c1, c0, 0                      ldr r0, =UPLLCON    mov r1, #UMDIV_48 /* USB时钟48MHz */    add r1, r1, #UPSDIV_48    str r1, [r0]     /*                * When you set MPLL&UPLL values, you have to set the UPLL     * value first and then the MPLL value. (Needs intervals     * approximately 7 NOP)     */               nop               nop               nop               nop               nop               nop               nop               ldr r0, =MPLLCON    mov r1, #MMDIV_405 /* cpu时钟 400MHz */    add r1, r1, #MPSDIV_405    str r1, [r0]# else              /* FCLK:HCLK:PCLK = 1:2:4 */    /* default FCLK is 120 MHz ! */    ldr r0, =CLKDIVN       mov r1, #3    str r1, [r0]#endif  /* CONFIG_S3C2440 */#endif  /* CONFIG_S3C24X0 */

tq2440.h中修改运行地址，支持u-boot直接烧录到SDRAM中运行：

- #define CONFIG_SYS_TEXT_BASE    0x0+ #define CONFIG_SYS_TEXT_BASE    0x33F80000

“CONFIG_SYS_TEXT_BASE 指定了代码的加载地址，待会编译好后生成可执行二进制文件
u-boot.bin，就要把u-boot.bin 下载到该地址。我们现在需要直接烧写进内存运行，而底层初始化代码还没移植，所以我们需要跳过底层初始化”

“经过加打印，问题定位在board.c中的board_init_r在调用mem_malloc_init函数时出了问题，他完成的
操作是将 malloc_start 标识的 malloc 区域清零，这里 malloc 区域的大小是 4MB+160KB，发现在清除
到2MB多的时候程序就挂了。
这个问题的原因好没有找到，等待解决。”

跳过底层初始化函数：

#define CONFIG_BOARD_EARLY_INIT_F+ #define CONFIG_SKIP_LOWLEVEL_INIT

在start.S文件中的cpu_init_crit就可以不用运行：

#ifndef CONFIG_SKIP_LOWLEVEL_INIT    bl  cpu_init_crit#endif

“如果没有定义CONFIG_SKIP_LOWLEVEL_INIT 就跳转 cpu_init_crit函数执行，该函数进行了一些底
层的初始化，比如内存。因为下面我们直接将u-boot下载到内存中运行，如果在内存中运行的同时再
初始化内存，那么内存中的数据代码会遭到破坏。”

编译首次运行

u-boot-2014.10]$ make

读者修改后编译肯定有地方不对，请一一排除错误。我这里修改后没有错误。生成u-boot.bin文件，将其拷贝到D:\kupan\temp\目录下(这个目录随便设置)，我们通过J-link将u-boot.bin烧录到0x33F80000位置，并运行。将USB转串口连接到开发板上，PC上的COM端口是COM4。

在J-link Commander界面中输入输入如下命令：

命令有：

J-link>h
J-link>loadbin D:\kupan\temp\u-boot.bin 0x33f80000
J-link>setpc 0x33f80000
J-link>g

如果Nand flash和Norflash上没有一个已经可以运行的u-boot时，仅仅将上面的执行文件烧录到0x33f80000位置石板够运行成功的，需要在0地址处有一个初始化程序，

将硬件环境设置在一个可以运行的环境中，下面是该初始化程序的代码和Makefile文件：

cat bootstrap.S：

/******************************************************************************************** *        File:  bootstrap.S  *     Version:  1.0.0 *   Copyright:  2011 (c) Guo Wenxue <Email: guowenxue@gmail.com QQ:281143292> * Description:  If we wanna debug u-boot by J-Link in external SDRAM, we must download this  *               bootstrap.bin file into s3c24x0 8K internal SRAM(Stepping Stone) and excute  *               first, which used to initialize the CPU and external SDRAM. Only after init  *               the SDRAM then we can debug u-boot in it. *   ChangeLog:  1, Release initial version on "Tue Jul 12 16:43:18 CST 2011" * *******************************************************************************************/#include "bootstrap.h"    .text    .align 2    .global _start_start:    /* set the cpu to SVC32 mode */    mrs r0, cpsr    bic r0, r0, #0x1f    orr r0, r0, #0xd3    msr cpsr, r0    /* Disable watchdog */    ldr r0, =S3C_WATCHDOG_BASE    mov r1, #0    str r1, [r0]    /* Disable Interrupt */    ldr r0, =S3C_INTERRUPT_BASE    mov r1, #0xffffffff    str r1, [r0, #INTMSK_OFFSET]    ldr r1, =0x000007ff    str r1, [r0, #INTSUBMSK_OFFSET]    /* http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0290g/Babjcgjg.html */    mov r0, #0    mcr p15, 0, r0, c7, c7, 0   /* flush v3/v4 cache, Invalidate ICache and DCache */    mcr p15, 0, r0, c8, c7, 0   /* flush v4 TLB */    /* disable MMU stuff and caches */    mrc p15, 0, r0, c1, c0, 0    bic r0, r0, #0x00002300     @ clear bits 13, 9:8 (--V- --RS)    bic r0, r0, #0x00000087     @ clear bits 7, 2:0 (B--- -CAM)     orr r0, r0, #0x00000002     @ set bit 2 (A) Align    orr r0, r0, #0x00001000     @ set bit 12 (I) I-Cache    mcr p15, 0, r0, c1, c0, 0 /*******************************************************************************************  * Init system clock and power, FCLK:HCLK:PCLK = 1:4:8   * Reference to S3C2440 datasheet: Chap 7 Clock&Power Management  *  * Initialize System Clock FCLK=400MHz HCLK=100MHz PCLK=50MHz  * FCLK is used by ARM920T  * HCLK is used for AHB bus, which is used by the ARM920T, the memory controller,  *      the interrupt controller, the LCD controller, the DMA and USB host block.  * PCLK is is used for APB bus,which is used by the peripherals such as WDT,IIS,I2C,  *      PWM timer,MMC interface,ADC,UART,GPIO,RTC and SPI.  ******************************************************************************************/    /*Set LOCKTIME as default value 0x00ffffff*/    ldr r0, =S3C_CLOCK_POWER_BASE    ldr r1, =0x00ffffff    str r1, [r0, #LOCKTIME_OFFSET]  /*******************************************************************************************  * Reference to S3C2440 datasheet: Chap 7-8 ~ Page 242  *  * Set the selection of Dividing Ratio between FCLK,HCLK and PCLK as FCLK:HCLK:PCLK = 1:4:8.  * This ratio is determined by HDIVN(here is 2) and PDIVN(here is 1) control register.  * Refer to the s3c2440 datasheet  *******************************************************************************************/    ldr r0, =S3C_CLOCK_POWER_BASE    mov r1, #5    str r1, [r0, #CLKDIVN_OFFSET]  /*Set Clock Divider*/    mrc p15, 0, r1, c1, c0, 0     orr r1, r1, #0xc0000000    mcr p15, 0, r1, c1, c0, 0  /***************************************************************************************  *  Reference to S3C2440 datasheet: Chap 7-20 ~ Page 254  *  *  Set MPLLCON(0x4C000004) register as:  *    [19:12]:  MDIV(Main Divider control)=0x7F (value set in MDIV_405)  *      [9:4]:  PDIV(Pre-devider control)=0x02  (value set in PSDIV_405)  *      [1:0]:  SDIV(Post divider control)=0x01 (value set in PSDIV_405)  *  *  MPLL(FCLK) = (2 * m * Fin)/(p * 2^s)  *  m=(MDIV+8), p=(PDIV+2), s=SDIV  *  *  So FCLK=((2*(127+8)*Fin)) / ((2+2)*2^1)  *         = (2*135*12MHz)/8  *         = 405MHz  *  For FCLK:HCLK:PCLK=1:4:8, so HCLK=100MHz, PCLK=50MHz  ***************************************************************************************/    mov r1, #S3C_CLOCK_POWER_BASE    mov r2, #MDIV_405    add r2, r2, #PSDIV_405    str r2, [r1, #MPLLCON_OFFSET]mem_init:    /* memory control configuration */    /* make r0 relative the current location so that it */    /* reads SMRDATA out of FLASH rather than memory ! */    ldr r0, =SMRDATA    ldr r1, =mem_init    sub r0, r0, r1    adr r3, mem_init       /* r3 <- current position of code   */    add r0, r0, r3  /*r0 =SMRDATA-mem_init+mem_init =SMRDATA*/    ldr r1, =BWSCON /* Bus Width Status Controller */    add r2, r0, #13*40:    ldr r3, [r0], #4    str r3, [r1], #4    cmp r2, r0    bne 0b    /*Set GPIO5 OUTPUT mode*/     ldr     r0, =GPBCON    ldr     r1, [r0]    bic     r1, r1, #0xC00       /*Set GPBCON for GPIO5 as 0x00 */    orr     r1, r1, #0x0400      /*Set GPBCON for GPIO5 as GPIOOUT, 0x01*/    str     r1, [r0]    ldr     r3, [r2]    bic     r3, r3, #(1<<LED0)  /*Clear bit 5, set GPB5 as low level*/    str     r3, [r2]    /* everything is fine now */dead_loop:    b   dead_loop    .ltorg/* the literal pools origin */SMRDATA:    .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))    .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))    .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))    .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))    .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))    .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))    .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))    .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))    .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))    .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)    .word 0xb2    .word 0x30    .word 0x30

bootstrap.h：

/* * ===================================================================================== * *       Filename:  bootstrap.h *        Version:  1.0.0 *         Author:  Guo Wenxue<Email: guowenxue@ghlsystems.com QQ:281143292> *      CopyRight:  2011 (C) Guo Wenxue *    Description:  Some Reigster address definition for bootstrap.S * ===================================================================================== */#define S3C_WATCHDOG_BASE       0x53000000#define S3C_INTERRUPT_BASE      0x4a000000#define SRCPND_OFFSET           0x00#define INTMOD_OFFSET           0x04#define INTMSK_OFFSET           0x08#define PRIORITY_OFFSET         0x0c#define INTPND_OFFSET           0x10#define INTOFFSET_OFFSET        0x14#define SUBSRCPND_OFFSET        0x18#define INTSUBMSK_OFFSET        0x1c#define S3C_CLOCK_POWER_BASE    0x4c000000#define LOCKTIME_OFFSET         0x00#define MPLLCON_OFFSET          0x04#define UPLLCON_OFFSET          0x08#define CLKCON_OFFSET           0x0c#define CLKSLOW_OFFSET          0x10#define CLKDIVN_OFFSET          0x14#define CAMDIVN_OFFSET          0x18#define BWSCON                          0x48000000#define MDIV_405                0x7f << 12#define PSDIV_405               0x21#define GPBCON   0x56000010#define GPBDAT   0x56000014#define GPBUP    0x56000018#define OUTPUT   0x01   /* Set GPIO port as output mode*/#define INPUT    0x00   /* Set GPIO port as input mode*/#define BEEP     0      /* On FL2440 board, LED0 use GPB0*/#define LED0     5      /* On FL2440 board, LED0 use GPB5*/#define LED1     6      /* On FL2440 board, LED0 use GPB6*/#define LED2     8      /* On FL2440 board, LED0 use GPB8*/#define LED3     10     /* On FL2440 board, LED0 use GPB10*//*  BWSCON */#define DW8             (0x0)#define DW16            (0x1)#define DW32            (0x2)#define WAIT            (0x1<<2)#define UBLB            (0x1<<3)#define B1_BWSCON       (DW16)#define B2_BWSCON       (DW16)#define B3_BWSCON       (DW16 + WAIT + UBLB)#define B4_BWSCON       (DW16)#define B5_BWSCON       (DW16)#define B6_BWSCON       (DW32)#define B7_BWSCON       (DW32)#define B0_Tacs         0x0#define B0_Tcos         0x0#define B0_Tacc         0x7#define B0_Tcoh         0x0#define B0_Tah          0x0#define B0_Tacp         0x0#define B0_PMC          0x0#define B1_Tacs         0x0#define B1_Tcos         0x0#define B1_Tacc         0x7#define B1_Tcoh         0x0#define B1_Tah          0x0#define B1_Tacp         0x0#define B1_PMC          0x0 #define B2_Tacs         0x0#define B2_Tcos         0x0#define B2_Tacc         0x7#define B2_Tcoh         0x0#define B2_Tah          0x0#define B2_Tacp         0x0#define B2_PMC          0x0#define B3_Tacs         0xc#define B3_Tcos         0x7#define B3_Tacc         0xf#define B3_Tcoh         0x1#define B3_Tah          0x0#define B3_Tacp         0x0#define B3_PMC          0x0#define B4_Tacs         0x0#define B4_Tcos         0x0#define B4_Tacc         0x7#define B4_Tcoh         0x0#define B4_Tah          0x0#define B4_Tacp         0x0#define B4_PMC          0x0#define B5_Tacs         0xc#define B5_Tcos         0x7#define B5_Tacc         0xf#define B5_Tcoh         0x1#define B5_Tah          0x0#define B5_Tacp         0x0#define B5_PMC          0x0#define B6_MT           0x3 /*  SDRAM */#define B6_Trcd         0x1#define B6_SCAN         0x1 /*  9bit */#define B7_MT           0x3 /*  SDRAM */#define B7_Trcd         0x1 /*  3clk */#define B7_SCAN         0x1 /*  9bit *//*  REFRESH parameter */#define REFEN           0x1 /*  Refresh enable */#define TREFMD          0x0 /*  CBR(CAS before RAS)/Auto refresh */#define Trc             0x3 /*  7clk */#define Tchr            0x2 /*  3clk */#if defined(CONFIG_S3C2440)#define Trp             0x2 /*  4clk */#define REFCNT          1012#else#define Trp             0x0 /*  2clk */#define REFCNT          0x0459#endif

Makefile文件：

# ***********************************************************************# *        File:  makefile# *     Version:  1.0.0# *   Copyright:  2011 (c) Guo Wenxue <guowenxue@gmail.com># * Description:  Makefile used to cross compile the ASM and C source code# *   ChangeLog:  1, Release initial version on "Mon Mar 21 21:09:52 CST 2011"# *# ***********************************************************************BINAME = bootstrapTEXTBASE = 0x33000000INST_PATH=${PWD}/../../../binCROSS = arm-linux-CC      = $(CROSS)gccLD      = $(CROSS)ldAR      = $(CROSS)arOBJCOPY = $(CROSS)objcopyOBJDUMP = $(CROSS)objdumpSTRIP   = $(CROSS)stripREADELF = $(CROSS)readelfCFLAGS  = -g -O2 -Wall -nostdinc -nostdlib -fno-builtinAFLAGS  = $(CFLAGS) -D__ASSEMBLY__LDFLAGS = -Ttext $(TEXTBASE)SRC_C   = $(wildcard *.c)SRC_S   = $(wildcard *.S)OBJ_C   = $(patsubst %.c,%.o,$(SRC_C)) OBJ_S   = $(patsubst %.S,%.o,$(SRC_S)) OBJ_ALL = $(OBJ_C) $(OBJ_S) .PHONY : all all: ${OBJ_ALL}        ${LD} $(LDFLAGS) -o ${BINAME}.elf ${OBJ_ALL}        ${OBJCOPY} -O binary -S ${BINAME}.elf ${BINAME}.bin        rm -f *.elf *.o        make install%.o: %.S                $(CC) $(AFLAGS) -c -o $@ $<%.o: %.c                $(CC) $(CFLAGS) -c -o $@ $<install:        cp -f ${BINAME}.bin ${INST_PATH} uninstall:        rm -f ${INST_PATH}/${BINAME}.bin  clean:        rm -f *.elf *.o        rm -f ${BINAME}.bin

初始化程序编译成功得到bootstrap.bin文件，将bootstrap.bin和u-boot.bin文件，通过J-link烧录到开发板中，记住要将OM[1:0] = 00，即开关置于Nandflash启动（这时候我们的代码还不支持Nand flash），这是因为ARM的4K的SRAM在OM[1:0] = 00时，会映射到ARM的0地址的起始位置。这时候bootstrap.bin文件才能烧录到0起始地址上。如果OM[1:0] ！= 00，即开关置于Norflash启动，这需要将bootstrap.bin文件烧录到Nor flash的0起始地址上。

烧录的方法可以根据文档操作：用JLINK烧写Uboot到NOR_FLASH配置过程_1

如果没有Norflash的读者，将OM[1:0] = 00。通过J-link的commander的命令形式将bootstrap.bin烧录到SRAM中，而将u-boot.bin文件烧录到SDRAM中，如下：

J-link>hJ-link>speed 12000J-link>loadbin D:\kupan\temp\bootstrap.bin 0J-link>setpc 0J-link>gJ-link>hJ-link>loadbin D:\kupan\temp\u-boot.bin 0x33f80000J-link>setpc 0x33f80000J-link>g

u-boot通过串口将调试信息打印出来，上面两种情况都可以有下面的结果，因为本文首先从支持Norflash启动，所以推荐大家将bootstrap.bin文件通过J-link软件烧录到Norflash中去(方法上面已经提到了)。

在secureCRT上打印信息如下：

如上面的打印信息，程序死在了这里：

Flash: *** failed ***
### ERROR ### Please RESET the board ###

开启打印调试信息

tq2440头文件中开启调试功能：

#ifndef __CONFIG_H#define __CONFIG_H+ #define DEBUG

重新编译、烧录、运行：打印信息：

U-Boot 2014.10 (Nov 08 2014 - 13:56:17)

U-Boot code: 33F80000 -> 33FAA200 BSS: -> 33FAF908
CPUID: 32440001
FCLK: 405.600 MHz
HCLK: 101.400 MHz
PCLK: 50.700 MHz
monitor len: 0002F908
ramsize: 04000000
TLB table from 33ff0000 to 33ff4000
Top of RAM usable for U-Boot at: 33ff0000
Reserving 190k for U-Boot at: 33fc0000
Reserving 4160k for malloc() at: 33bb0000
Reserving 28 Bytes for Board Info at: 33baffe4
Reserving 160 Bytes for Global Data at: 33baff44
New Stack Pointer is: 33baff38
RAM Configuration:
Bank #0: 30000000 64 MiB
relocation Offset is: 00040000
WARNING: Caches not enabled
monitor flash len: 0002F110
Now running in RAM - U-Boot at: 33fc0000
Flash: fwc addr 00000000 cmd f0 00f0 16bit x 16 bit
fwc addr 0000aaaa cmd aa 00aa 16bit x 16 bit
fwc addr 00005554 cmd 55 0055 16bit x 16 bit
fwc addr 0000aaaa cmd 90 0090 16bit x 16 bit
fwc addr 00000000 cmd f0 00f0 16bit x 16 bit
JEDEC PROBE: ID 1c 2249 0
fwc addr 00000000 cmd ff 00ff 16bit x 16 bit
fwc addr 00000000 cmd 90 0090 16bit x 16 bit
fwc addr 00000000 cmd ff 00ff 16bit x 16 bit
JEDEC PROBE: ID 12 ea00 0
*** failed ***
### ERROR ### Please RESET the board ###

这里挂了！

NOR flash支持

在代码中定位找到这一字符串的位置在文件arch/arm/lib/board.c中：

#if !defined(CONFIG_SYS_NO_FLASH)    puts("Flash: ");    flash_size = flash_init();    if (flash_size > 0) {# ifdef CONFIG_SYS_FLASH_CHECKSUM        print_size(flash_size, "");        /*         * Compute and print flash CRC if flashchecksum is set to 'y'         *         * NOTE: Maybe we should add some WATCHDOG_RESET()? XXX         */        if (getenv_yesno("flashchecksum") == 1) {            printf("  CRC: %08X", crc32(0,                (const unsigned char *) CONFIG_SYS_FLASH_BASE,                flash_size));        }        putc('\n');# else  /* !CONFIG_SYS_FLASH_CHECKSUM */        print_size(flash_size, "\n");# endif /* CONFIG_SYS_FLASH_CHECKSUM */    } else {        puts(failed);        hang();    }#endif

在函数flash初始化失败，flash_init函数在drivers/mtd/cfi_flash.c文件中，flash_detect_legacy函数用于探测flash的信息，jedec_flash_match函数将探测到的数据与jedec_table表中的信息进行匹配查找，如果没有找到这个型号的就会flash_init失败。

jiedec_table表在drivers/mtd/jedec_flash.c文件中定义。在jedec_table表中增加TQ2440开发板的NOR FLASH(EN29LV160AB)芯片内容：

jiedec_table后面加上：

#ifdef CONFIG_SYS_FLASH_LEGACY_1024Kx16    { /* TQ2440 ENV29LV160AB */        .mfr_id     = 0x1C, /* manufacturer_id */        .dev_id     = 0x2249, /* device_id */        .name       = "EON EN29LV160AB",        .uaddr      = { /* 因为NOR FLASH的ADDR0 接到了S3C2440的ADDR1 */            [1] = MTD_UADDR_0x0555_0x02AA /* x16 */        },        .DevSize    = SIZE_2MiB,        .CmdSet     = P_ID_AMD_STD,        .NumEraseRegions = 4,        .regions    = {            ERASEINFO(0x04000, 1),            ERASEINFO(0x02000, 2),            ERASEINFO(0x08000, 1),            ERASEINFO(0x10000, 31),        }    },#endif

tq2440.h文件中定义该宏：

- #define CONFIG_SYS_FLASH_LEGACY_512Kx16+ #define CONFIG_SYS_FLASH_LEGACY_1024Kx16

重新编译、烧录、运行：打印信息：

U-Boot 2014.10 (Nov 08 2014 - 15:50:51)
。。。。。。
JEDEC PROBE: ID 1c 2249 0
Found JEDEC Flash: EON EN29LV160AB
unlock address index 1
unlock addresses are 0x555/0x2aa
erase_region_count = 1 erase_region_size = 16384
erase_region_count = 2 erase_region_size = 8192
erase_region_count = 1 erase_region_size = 32768
erase_region_count = 31 erase_region_size = 65536
ERROR: too many flash sectors
flash_protect ON: from 0x00000000 to 0x0002EFE7
protect on 0
protect on 1
protect on 2
protect on 3
protect on 4
protect on 5
flash_protect ON: from 0x00070000 to 0x0007FFFF
protect on 10
2 MiB
*** Warning - bad CRC, using default environment

Destroy Hash Table: 33fe8ab8 table = 00000000
Create Hash Table: N=75
INSERT: table 33fe8ab8, filled 1/79 rv 33bb0238 ==> name="bootdelay" value="5"
INSERT: table 33fe8ab8, filled 2/79 rv 33bb00f8 ==> name="baudrate" value="115200"
INSERT: table 33fe8ab8, filled 3/79 rv 33bb00a8 ==> name="ipaddr" value="10.0.0.110"
INSERT: table 33fe8ab8, filled 4/79 rv 33bb0260 ==> name="serverip" value="10.0.0.1"
INSERT: table 33fe8ab8, filled 5/79 rv 33bb04f4 ==> name="netmask" value="255.255.255.0"
INSERT: free(data = 33bb0008)
INSERT: done
In: serial
Out: serial
Err: serial
Initial value for argc=3
Final value for argc=3
Initial value for argc=3
Final value for argc=3
Initial value for argc=3
Final value for argc=3
Net: No ethernet found.
Warning: Your board does not use generic board. Please read
doc/README.generic-board and take action. Boards not
upgraded by the late 2014 may break or be removed.
### main_loop entered: bootdelay=5

### main_loop: bootcmd="<UNDEFINED>"
TQ2440 #

“ERROR: too many flash sectors”在drivers/mtd/jedec_flash.c文件中：

if (sect_cnt >= CONFIG_SYS_MAX_FLASH_SECT) {                printf("ERROR: too many flash sectors\n");                break;}

CONFIG_SYS_MAX_FLASH_SECT的值在tq2440.h文件中定义为：

- #define CONFIG_SYS_MAX_FLASH_SECT   (19)+ #define CONFIG_SYS_MAX_FLASH_SECT   (35)

改为35，35的原因是：

EN29LV160AB手册上说：

ERASEINFO(16*1024, 1), /* 16KB的一块*/
ERASEINFO(8*1024 , 2), /* 8KB 的两块*/

ERASEINFO(32*1024, 1), /* 32KB的一块*/
ERASEINFO(64*1024, 31), / * 64KB的31 块*/
有35个块。

nor flash中还有一些块写了保护，暂时放着。

重新编译、烧录、运行，就没有这个错误了。

明天继续。

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