FPGA Verilog语言实现数字钟

  FPGA第一次练手

 仅有基本的计时功能，其他的功能正在赶来

程序如下：

module column_scan_module
(
    CLK, RSTn, Column_Scan_Sig,Row_Scan_Sig
);
    
input CLK;
input RSTn;
output [5:0]Column_Scan_Sig;
output [7:0]Row_Scan_Sig;
 
/*****************************/
 
  parameter T4MS = 18'd19_9999;
 
/*****************************/
 
reg [18:0]Count1;
 
always @ ( posedge CLK or negedge RSTn )
    if( !RSTn )
     Count1 <= 18'd0;
 else if( Count1 == T4MS )
     Count1 <= 18'd0;
 else
     Count1 <= Count1 + 1'b1;

/******************************/
 
reg [2:0]t;
 
always @ ( posedge CLK or negedge RSTn )
    if( !RSTn )
     t <= 3'd0;
 else if( t == 3'd6 )
     t <= 3'd0;
 else if( Count1 == T4MS )
     t <= t + 1'b1;

    /*********************************/
 
reg [5:0]rColumn_Scan;
 
always @ ( posedge CLK or negedge RSTn )
    if( !RSTn )
     rColumn_Scan <= 6'b111111;
 else if( Count1 == T4MS )
     case( t )

   3'd0 : rColumn_Scan <= 6'b111110;
3'd1 : rColumn_Scan <= 6'b111101;
   3'd2 : rColumn_Scan <= 6'b111011;
3'd3 : rColumn_Scan <= 6'b110111;
3'd4 : rColumn_Scan <= 6'b101111;
3'd5 : rColumn_Scan <= 6'b011111;
endcase  

 /***************************************/
 
 assign Column_Scan_Sig =  rColumn_Scan;
 
 
/****************************************/ 

parameter T1S = 28'd49_999_999;

 /*****************Second**********************/
 
reg [27:0]Count2;
 
always @ ( posedge CLK or negedge RSTn )
    if( !RSTn )
     Count2 <= 28'd0;
 else if( Count2 == T1S )
     Count2 <= 28'd0;
 else
     Count2 <= Count2 + 1'b1; 

  /***************************************/
 
reg [7:0]Counter_Sec;
reg [7:0]Counter_Min;

always @ ( posedge CLK or negedge RSTn )
    if( !RSTn )
     begin 
         Counter_Sec <= 8'd0;
  end
 else if( Count2 == T1S )
     begin
   Counter_Sec <= Counter_Sec + 1'd1;
      if( Counter_Sec == 8'd59 ) 
begin Counter_Sec <= 8'd0;
      Counter_Min <= Counter_Min + 1'd1;
      if ( Counter_Min == 8'd59 )
   Counter_Min <= 8'd0;
end
end

 /***************************************/
 
reg [31:0]rTen_Sec;
reg [31:0]rOne_Sec;
 
always @ ( posedge CLK or negedge RSTn )
    if( !RSTn )
     begin
   rTen_Sec <= 32'd0;
rOne_Sec <= 32'd0;
end
else 
   begin
    rTen_Sec <= Counter_Sec / 10;
 rOne_Sec <= Counter_Sec % 10;
end

/***********************************/
 
reg [31:0]rTen_Min;
reg [31:0]rOne_Min;
 
always @ ( posedge CLK or negedge RSTn )
    if( !RSTn )
     begin
   rTen_Min <= 32'd0;
rOne_Min <= 32'd0;
end
else 
   begin
    rTen_Min <= Counter_Min / 10;
 rOne_Min <= Counter_Min % 10;
end
 
 
 
 /****************************************/ /****************************************/
 
reg [7:0]rTen_SMG_Sec;


always @ ( posedge CLK or negedge RSTn )
    if( !RSTn )
     begin
   rTen_SMG_Sec <= 8'b1111_1111;
end
        else 
      case( rTen_Sec )
          
 4'd0 : rTen_SMG_Sec  <= _0;
 4'd1 : rTen_SMG_Sec  <= _1;
 4'd2 : rTen_SMG_Sec  <= _2;
 4'd3 : rTen_SMG_Sec  <= _3;
 4'd4 : rTen_SMG_Sec  <= _4;
 4'd5 : rTen_SMG_Sec  <= _5;
 4'd6 : rTen_SMG_Sec  <= _6;
 4'd7 : rTen_SMG_Sec  <= _7;
 4'd8 : rTen_SMG_Sec  <= _8;
 4'd9 : rTen_SMG_Sec  <= _9;
 
endcase
 
/***************************************/   
 
reg [7:0]rOne_SMG_Sec;


always @ ( posedge CLK or negedge RSTn )
    if( !RSTn )
     begin
   rOne_SMG_Sec <= 8'b1111_1111;
end
        else 
      case( rOne_Sec )
          
 4'd0 : rOne_SMG_Sec  <= _0;
 4'd1 : rOne_SMG_Sec  <= _1;
 4'd2 : rOne_SMG_Sec  <= _2;
 4'd3 : rOne_SMG_Sec  <= _3;
 4'd4 : rOne_SMG_Sec  <= _4;
 4'd5 : rOne_SMG_Sec  <= _5;
 4'd6 : rOne_SMG_Sec  <= _6;
 4'd7 : rOne_SMG_Sec  <= _7;
 4'd8 : rOne_SMG_Sec  <= _8;
 4'd9 : rOne_SMG_Sec  <= _9;
 
endcase  
 
/***************************************/


 
reg [7:0]rTen_SMG_Min;


always @ ( posedge CLK or negedge RSTn )
    if( !RSTn )
     begin
   rTen_SMG_Min <= 8'b1111_1111;
end
        else 
      case( rTen_Min )
          
 4'd0 : rTen_SMG_Min  <= _0;
 4'd1 : rTen_SMG_Min  <= _1;
 4'd2 : rTen_SMG_Min  <= _2;
 4'd3 : rTen_SMG_Min  <= _3;
 4'd4 : rTen_SMG_Min  <= _4;
 4'd5 : rTen_SMG_Min  <= _5;
 4'd6 : rTen_SMG_Min  <= _6;
 4'd7 : rTen_SMG_Min  <= _7;
 4'd8 : rTen_SMG_Min  <= _8;
 4'd9 : rTen_SMG_Min  <= _9;
 
endcase
 
/***************************************/


 
reg [7:0]rOne_SMG_Min;


always @ ( posedge CLK or negedge RSTn )
    if( !RSTn )
     begin
   rOne_SMG_Min <= 8'b1111_1111;
end
        else 
      case( rOne_Min )
          
 4'd0 : rOne_SMG_Min  <= _0;
 4'd1 : rOne_SMG_Min  <= _1;
 4'd2 : rOne_SMG_Min  <= _2;
 4'd3 : rOne_SMG_Min  <= _3;
 4'd4 : rOne_SMG_Min  <= _4;
 4'd5 : rOne_SMG_Min  <= _5;
 4'd6 : rOne_SMG_Min  <= _6;
 4'd7 : rOne_SMG_Min  <= _7;
 4'd8 : rOne_SMG_Min  <= _8;
 4'd9 : rOne_SMG_Min  <= _9;
 
endcase
 
/***************************************/
 
 reg [7:0]rData;

    always @ ( posedge CLK or negedge RSTn )
    if( !RSTn )
    rData <= 8'd0;
else  if( Count1 == T4MS )
     case( t )

         3'd0 : rData <= rOne_SMG_Sec;
3'd1 : rData <= rTen_SMG_Sec; 
3'd2 : rData <= rOne_SMG_Min;
3'd3 : rData <= rTen_SMG_Min; 
3'd4 : rData <= 8'b1001_1001;
3'd5 : rData <= 8'b1001_0010; 

endcase

/***************************************/
 
parameter _0 = 8'b1100_0000, _1 = 8'b1111_1001, _2 = 8'b1010_0100, 
          _3 = 8'b1011_0000, _4 = 8'b1001_1001, _5 = 8'b1001_0010, 
 _6 = 8'b1000_0010, _7 = 8'b1111_1000, _8 = 8'b1000_0000,
 _9 = 8'b1001_0000;
 
/***************************************/
 
     assign Row_Scan_Sig = rData;




endmodule

亲测成功   Cyclone IVE 芯片 CE4CP6F17C8