FPGA Verilog实现数字钟2 校时校分蜂鸣器功能
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/************************************************
Design by Romy
2015.10.05
**************************************************/
module column_scan_module
(
CLK, RSTn,
Column_Scan_Sig,Row_Scan_Sig, EN, S1,S2,spk
);
input CLK;
input RSTn;
input EN;
input S1;
input S2;
output spk;
output [5:0]Column_Scan_Sig;
output [7:0]Row_Scan_Sig;
/*****************************/
parameter T4MS = 18'd19_9999;
/*************** Clock **************/
/*************** Clock **************/
reg [18:0]Count1;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
Count1 <= 18'd0;
else if( Count1 == T4MS )
Count1 <= 18'd0;
else
Count1 <= Count1 + 1'b1;
/************** SMG choose ****************/
/************** SMG choose ****************/
reg [2:0]t;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
t <= 3'd0;
else if( t == 3'd6 )
t <= 3'd0;
else if( Count1 == T4MS )
t <= t + 1'b1;
/************** SMG choose ****************/
reg [5:0]rColumn_Scan;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
rColumn_Scan <= 6'b111111;
else if( Count1 == T4MS )
case( t )
3'd0 : rColumn_Scan <= 6'b111110;
3'd1 : rColumn_Scan <= 6'b111101;
3'd2 : rColumn_Scan <= 6'b111011;
3'd3 : rColumn_Scan <= 6'b110111;
3'd4 : rColumn_Scan <= 6'b101111;
3'd5 : rColumn_Scan <= 6'b011111;
endcase
/***************************************/
assign Column_Scan_Sig = rColumn_Scan;
/****************** Counter *********************/
/***************** Counter **********************/
parameter T1S = 28'd49_999_999;
/*****************Second**********************/
reg [27:0]Count2;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
Count2 <= 28'd0;
else if( Count2 == T1S )
Count2 <= 28'd0;
else
Count2 <= Count2 + 1'b1;
/***************** Counter **********************/
reg [7:0]Counter_Sec;
reg [7:0]Counter_Min;
reg [7:0]Counter_Hou;
/***************** Setting **********************/
parameter T200MS = 28'd99_999_99;
/*****************Second**********************/
reg [27:0]Count3;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
Count3 <= 28'd0;
else if( Count3 == T200MS )
Count3 <= 28'd0;
else
Count3 <= Count3 + 1'b1;
/***************** Setting **********************/
always @(posedge CLK or negedge RSTn )
if(!RSTn) begin Counter_Sec <=0;Counter_Min <= 0; Counter_Hou <= 0; end
// else if( EN )
// begin
else if(!S1)
begin
if ( Count3 == T200MS )
begin
if( Counter_Hou == 8'd23 )
Counter_Hou <=0;
else if ( Count3 == T200MS )
Counter_Hou <= Counter_Hou + 1'd1;
end
end
else if(!S2)
begin
if ( Count3 == T200MS )
begin
if(Counter_Min == 8'd59 ) Counter_Min <=0;
else
Counter_Min <= Counter_Min + 1'd1;
end
end
//end
else if( Count2 == T1S )
begin
Counter_Sec <= Counter_Sec + 1'd1;
if( Counter_Sec == 8'd59 )
begin
Counter_Sec <= 8'd0;
Counter_Min <= Counter_Min + 1'd1;
if ( Counter_Min == 8'd59 )
begin
Counter_Min <= 8'd0;
Counter_Hou <= Counter_Hou + 1'd1;
if ( Counter_Hou == 8'd23 )
Counter_Hou <= 8'd0;
end
end
end
else
begin
Counter_Sec <= Counter_Sec;
Counter_Min <= Counter_Min;
end
/* if( !RSTn )
begin
Counter_Sec <= 8'd0;
end
else if( Count2 == T1S )
begin
Counter_Sec <= Counter_Sec + 1'd1;
if( Counter_Sec == 8'd59 )
begin
Counter_Sec <= 8'd0;
Counter_Min <= Counter_Min + 1'd1;
if ( Counter_Min == 8'd59 )
begin
Counter_Min <= 8'd0;
Counter_Hou <= Counter_Hou + 1'd1;
if ( Counter_Hou == 8'd23 )
Counter_Hou <= 8'd0;
end
end
end
/*************** buzzer ************************/
reg spk;
always @(posedge CLK or negedge RSTn ) //
if(!RSTn)
spk <= 0;
else
begin
if( Counter_Min == 8'd1 && Counter_Sec == 8'd0 ) begin spk<= 0 ;end
else if( Counter_Hou == 8'd1 && Counter_Min == 8'd0 ) begin spk<= 0 ; end
else spk <= 1;
end
reg [31:0]rTen_Sec;
reg [31:0]rOne_Sec;
/*************** Second ************************/
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
begin
rTen_Sec <= 32'd0;
rOne_Sec <= 32'd0;
end
else
begin
rTen_Sec <= Counter_Sec / 10;
rOne_Sec <= Counter_Sec % 10;
end
/**************** Minute *******************/
reg [31:0]rTen_Min;
reg [31:0]rOne_Min;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
begin
rTen_Min <= 32'd0;
rOne_Min <= 32'd0;
end
else
begin
rTen_Min <= Counter_Min / 10;
rOne_Min <= Counter_Min % 10;
end
/**************** Hour *******************/
reg [31:0]rTen_Hou;
reg [31:0]rOne_Hou;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
begin
rTen_Hou <= 32'd0;
rOne_Hou <= 32'd0;
end
else
begin
rTen_Hou <= Counter_Hou / 10;
rOne_Hou <= Counter_Hou % 10;
end
/******************** display **********************/
/******************** display **********************/
/******************** Second **********************/
reg [7:0]rTen_SMG_Sec;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
begin
rTen_SMG_Sec <= 8'b1111_1111;
end
else
case( rTen_Sec )
4'd0 : rTen_SMG_Sec <= _0;
4'd1 : rTen_SMG_Sec <= _1;
4'd2 : rTen_SMG_Sec <= _2;
4'd3 : rTen_SMG_Sec <= _3;
4'd4 : rTen_SMG_Sec <= _4;
4'd5 : rTen_SMG_Sec <= _5;
4'd6 : rTen_SMG_Sec <= _6;
4'd7 : rTen_SMG_Sec <= _7;
4'd8 : rTen_SMG_Sec <= _8;
4'd9 : rTen_SMG_Sec <= _9;
endcase
/***************************************/
reg [7:0]rOne_SMG_Sec;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
begin
rOne_SMG_Sec <= 8'b1111_1111;
end
else
case( rOne_Sec )
4'd0 : rOne_SMG_Sec <= _0;
4'd1 : rOne_SMG_Sec <= _1;
4'd2 : rOne_SMG_Sec <= _2;
4'd3 : rOne_SMG_Sec <= _3;
4'd4 : rOne_SMG_Sec <= _4;
4'd5 : rOne_SMG_Sec <= _5;
4'd6 : rOne_SMG_Sec <= _6;
4'd7 : rOne_SMG_Sec <= _7;
4'd8 : rOne_SMG_Sec <= _8;
4'd9 : rOne_SMG_Sec <= _9;
endcase
/******************** Minute *******************/
reg [7:0]rTen_SMG_Min;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
begin
rTen_SMG_Min <= 8'b1111_1111;
end
else
case( rTen_Min )
4'd0 : rTen_SMG_Min <= _0;
4'd1 : rTen_SMG_Min <= _1;
4'd2 : rTen_SMG_Min <= _2;
4'd3 : rTen_SMG_Min <= _3;
4'd4 : rTen_SMG_Min <= _4;
4'd5 : rTen_SMG_Min <= _5;
4'd6 : rTen_SMG_Min <= _6;
4'd7 : rTen_SMG_Min <= _7;
4'd8 : rTen_SMG_Min <= _8;
4'd9 : rTen_SMG_Min <= _9;
endcase
/***************************************/
reg [7:0]rOne_SMG_Min;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
begin
rOne_SMG_Min <= 8'b1111_1111;
end
else
case( rOne_Min )
4'd0 : rOne_SMG_Min <= _0;
4'd1 : rOne_SMG_Min <= _1;
4'd2 : rOne_SMG_Min <= _2;
4'd3 : rOne_SMG_Min <= _3;
4'd4 : rOne_SMG_Min <= _4;
4'd5 : rOne_SMG_Min <= _5;
4'd6 : rOne_SMG_Min <= _6;
4'd7 : rOne_SMG_Min <= _7;
4'd8 : rOne_SMG_Min <= _8;
4'd9 : rOne_SMG_Min <= _9;
endcase
/******************** Hour *******************/
reg [7:0]rTen_SMG_Hou;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
begin
rTen_SMG_Hou <= 8'b1111_1111;
end
else
case( rTen_Hou )
4'd0 : rTen_SMG_Hou <= _0;
4'd1 : rTen_SMG_Hou <= _1;
4'd2 : rTen_SMG_Hou <= _2;
4'd3 : rTen_SMG_Hou <= _3;
4'd4 : rTen_SMG_Hou <= _4;
4'd5 : rTen_SMG_Hou <= _5;
4'd6 : rTen_SMG_Hou <= _6;
4'd7 : rTen_SMG_Hou <= _7;
4'd8 : rTen_SMG_Hou <= _8;
4'd9 : rTen_SMG_Hou <= _9;
endcase
/***************************************/
reg [7:0]rOne_SMG_Hou;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
begin
rOne_SMG_Hou <= 8'b1111_1111;
end
else
case( rOne_Hou )
4'd0 : rOne_SMG_Hou <= _0;
4'd1 : rOne_SMG_Hou <= _1;
4'd2 : rOne_SMG_Hou <= _2;
4'd3 : rOne_SMG_Hou <= _3;
4'd4 : rOne_SMG_Hou <= _4;
4'd5 : rOne_SMG_Hou <= _5;
4'd6 : rOne_SMG_Hou <= _6;
4'd7 : rOne_SMG_Hou <= _7;
4'd8 : rOne_SMG_Hou <= _8;
4'd9 : rOne_SMG_Hou <= _9;
endcase
/***************** Encoder **********************/
/******************** Encoder *******************/
reg [7:0]rData;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
rData <= 8'd0;
else if( Count1 == T4MS )
case( t )
3'd0 : rData <= rOne_SMG_Sec;
3'd1 : rData <= rTen_SMG_Sec;
3'd2 : rData <= rOne_SMG_Min;
3'd3 : rData <= rTen_SMG_Min;
3'd4 : rData <= rOne_SMG_Hou;
3'd5 : rData <= rTen_SMG_Hou;
endcase
/***************************************/
parameter _0 = 8'b1100_0000, _1 = 8'b1111_1001, _2 = 8'b1010_0100,
_3 = 8'b1011_0000, _4 = 8'b1001_1001, _5 = 8'b1001_0010,
_6 = 8'b1000_0010, _7 = 8'b1111_1000, _8 = 8'b1000_0000,
_9 = 8'b1001_0000;
/***************************************/
assign Row_Scan_Sig = rData;
/***************************************/
/* always @(posedge CLK or negedge RSTn ) //????????
begin
if( Counter_Sec == 8'd10) begin spk<= CLK ;end
else if( Counter_Min == 8'd1) spk<= CLK ;
else spk<=0;
end */
endmodule
Design by Romy
2015.10.05
**************************************************/
module column_scan_module
(
CLK, RSTn,
Column_Scan_Sig,Row_Scan_Sig, EN, S1,S2,spk
);
input CLK;
input RSTn;
input EN;
input S1;
input S2;
output spk;
output [5:0]Column_Scan_Sig;
output [7:0]Row_Scan_Sig;
/*****************************/
parameter T4MS = 18'd19_9999;
/*************** Clock **************/
/*************** Clock **************/
reg [18:0]Count1;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
Count1 <= 18'd0;
else if( Count1 == T4MS )
Count1 <= 18'd0;
else
Count1 <= Count1 + 1'b1;
/************** SMG choose ****************/
/************** SMG choose ****************/
reg [2:0]t;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
t <= 3'd0;
else if( t == 3'd6 )
t <= 3'd0;
else if( Count1 == T4MS )
t <= t + 1'b1;
/************** SMG choose ****************/
reg [5:0]rColumn_Scan;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
rColumn_Scan <= 6'b111111;
else if( Count1 == T4MS )
case( t )
3'd0 : rColumn_Scan <= 6'b111110;
3'd1 : rColumn_Scan <= 6'b111101;
3'd2 : rColumn_Scan <= 6'b111011;
3'd3 : rColumn_Scan <= 6'b110111;
3'd4 : rColumn_Scan <= 6'b101111;
3'd5 : rColumn_Scan <= 6'b011111;
endcase
/***************************************/
assign Column_Scan_Sig = rColumn_Scan;
/****************** Counter *********************/
/***************** Counter **********************/
parameter T1S = 28'd49_999_999;
/*****************Second**********************/
reg [27:0]Count2;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
Count2 <= 28'd0;
else if( Count2 == T1S )
Count2 <= 28'd0;
else
Count2 <= Count2 + 1'b1;
/***************** Counter **********************/
reg [7:0]Counter_Sec;
reg [7:0]Counter_Min;
reg [7:0]Counter_Hou;
/***************** Setting **********************/
parameter T200MS = 28'd99_999_99;
/*****************Second**********************/
reg [27:0]Count3;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
Count3 <= 28'd0;
else if( Count3 == T200MS )
Count3 <= 28'd0;
else
Count3 <= Count3 + 1'b1;
/***************** Setting **********************/
always @(posedge CLK or negedge RSTn )
if(!RSTn) begin Counter_Sec <=0;Counter_Min <= 0; Counter_Hou <= 0; end
// else if( EN )
// begin
else if(!S1)
begin
if ( Count3 == T200MS )
begin
if( Counter_Hou == 8'd23 )
Counter_Hou <=0;
else if ( Count3 == T200MS )
Counter_Hou <= Counter_Hou + 1'd1;
end
end
else if(!S2)
begin
if ( Count3 == T200MS )
begin
if(Counter_Min == 8'd59 ) Counter_Min <=0;
else
Counter_Min <= Counter_Min + 1'd1;
end
end
//end
else if( Count2 == T1S )
begin
Counter_Sec <= Counter_Sec + 1'd1;
if( Counter_Sec == 8'd59 )
begin
Counter_Sec <= 8'd0;
Counter_Min <= Counter_Min + 1'd1;
if ( Counter_Min == 8'd59 )
begin
Counter_Min <= 8'd0;
Counter_Hou <= Counter_Hou + 1'd1;
if ( Counter_Hou == 8'd23 )
Counter_Hou <= 8'd0;
end
end
end
else
begin
Counter_Sec <= Counter_Sec;
Counter_Min <= Counter_Min;
end
/* if( !RSTn )
begin
Counter_Sec <= 8'd0;
end
else if( Count2 == T1S )
begin
Counter_Sec <= Counter_Sec + 1'd1;
if( Counter_Sec == 8'd59 )
begin
Counter_Sec <= 8'd0;
Counter_Min <= Counter_Min + 1'd1;
if ( Counter_Min == 8'd59 )
begin
Counter_Min <= 8'd0;
Counter_Hou <= Counter_Hou + 1'd1;
if ( Counter_Hou == 8'd23 )
Counter_Hou <= 8'd0;
end
end
end
/*************** buzzer ************************/
reg spk;
always @(posedge CLK or negedge RSTn ) //
if(!RSTn)
spk <= 0;
else
begin
if( Counter_Min == 8'd1 && Counter_Sec == 8'd0 ) begin spk<= 0 ;end
else if( Counter_Hou == 8'd1 && Counter_Min == 8'd0 ) begin spk<= 0 ; end
else spk <= 1;
end
reg [31:0]rTen_Sec;
reg [31:0]rOne_Sec;
/*************** Second ************************/
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
begin
rTen_Sec <= 32'd0;
rOne_Sec <= 32'd0;
end
else
begin
rTen_Sec <= Counter_Sec / 10;
rOne_Sec <= Counter_Sec % 10;
end
/**************** Minute *******************/
reg [31:0]rTen_Min;
reg [31:0]rOne_Min;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
begin
rTen_Min <= 32'd0;
rOne_Min <= 32'd0;
end
else
begin
rTen_Min <= Counter_Min / 10;
rOne_Min <= Counter_Min % 10;
end
/**************** Hour *******************/
reg [31:0]rTen_Hou;
reg [31:0]rOne_Hou;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
begin
rTen_Hou <= 32'd0;
rOne_Hou <= 32'd0;
end
else
begin
rTen_Hou <= Counter_Hou / 10;
rOne_Hou <= Counter_Hou % 10;
end
/******************** display **********************/
/******************** display **********************/
/******************** Second **********************/
reg [7:0]rTen_SMG_Sec;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
begin
rTen_SMG_Sec <= 8'b1111_1111;
end
else
case( rTen_Sec )
4'd0 : rTen_SMG_Sec <= _0;
4'd1 : rTen_SMG_Sec <= _1;
4'd2 : rTen_SMG_Sec <= _2;
4'd3 : rTen_SMG_Sec <= _3;
4'd4 : rTen_SMG_Sec <= _4;
4'd5 : rTen_SMG_Sec <= _5;
4'd6 : rTen_SMG_Sec <= _6;
4'd7 : rTen_SMG_Sec <= _7;
4'd8 : rTen_SMG_Sec <= _8;
4'd9 : rTen_SMG_Sec <= _9;
endcase
/***************************************/
reg [7:0]rOne_SMG_Sec;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
begin
rOne_SMG_Sec <= 8'b1111_1111;
end
else
case( rOne_Sec )
4'd0 : rOne_SMG_Sec <= _0;
4'd1 : rOne_SMG_Sec <= _1;
4'd2 : rOne_SMG_Sec <= _2;
4'd3 : rOne_SMG_Sec <= _3;
4'd4 : rOne_SMG_Sec <= _4;
4'd5 : rOne_SMG_Sec <= _5;
4'd6 : rOne_SMG_Sec <= _6;
4'd7 : rOne_SMG_Sec <= _7;
4'd8 : rOne_SMG_Sec <= _8;
4'd9 : rOne_SMG_Sec <= _9;
endcase
/******************** Minute *******************/
reg [7:0]rTen_SMG_Min;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
begin
rTen_SMG_Min <= 8'b1111_1111;
end
else
case( rTen_Min )
4'd0 : rTen_SMG_Min <= _0;
4'd1 : rTen_SMG_Min <= _1;
4'd2 : rTen_SMG_Min <= _2;
4'd3 : rTen_SMG_Min <= _3;
4'd4 : rTen_SMG_Min <= _4;
4'd5 : rTen_SMG_Min <= _5;
4'd6 : rTen_SMG_Min <= _6;
4'd7 : rTen_SMG_Min <= _7;
4'd8 : rTen_SMG_Min <= _8;
4'd9 : rTen_SMG_Min <= _9;
endcase
/***************************************/
reg [7:0]rOne_SMG_Min;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
begin
rOne_SMG_Min <= 8'b1111_1111;
end
else
case( rOne_Min )
4'd0 : rOne_SMG_Min <= _0;
4'd1 : rOne_SMG_Min <= _1;
4'd2 : rOne_SMG_Min <= _2;
4'd3 : rOne_SMG_Min <= _3;
4'd4 : rOne_SMG_Min <= _4;
4'd5 : rOne_SMG_Min <= _5;
4'd6 : rOne_SMG_Min <= _6;
4'd7 : rOne_SMG_Min <= _7;
4'd8 : rOne_SMG_Min <= _8;
4'd9 : rOne_SMG_Min <= _9;
endcase
/******************** Hour *******************/
reg [7:0]rTen_SMG_Hou;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
begin
rTen_SMG_Hou <= 8'b1111_1111;
end
else
case( rTen_Hou )
4'd0 : rTen_SMG_Hou <= _0;
4'd1 : rTen_SMG_Hou <= _1;
4'd2 : rTen_SMG_Hou <= _2;
4'd3 : rTen_SMG_Hou <= _3;
4'd4 : rTen_SMG_Hou <= _4;
4'd5 : rTen_SMG_Hou <= _5;
4'd6 : rTen_SMG_Hou <= _6;
4'd7 : rTen_SMG_Hou <= _7;
4'd8 : rTen_SMG_Hou <= _8;
4'd9 : rTen_SMG_Hou <= _9;
endcase
/***************************************/
reg [7:0]rOne_SMG_Hou;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
begin
rOne_SMG_Hou <= 8'b1111_1111;
end
else
case( rOne_Hou )
4'd0 : rOne_SMG_Hou <= _0;
4'd1 : rOne_SMG_Hou <= _1;
4'd2 : rOne_SMG_Hou <= _2;
4'd3 : rOne_SMG_Hou <= _3;
4'd4 : rOne_SMG_Hou <= _4;
4'd5 : rOne_SMG_Hou <= _5;
4'd6 : rOne_SMG_Hou <= _6;
4'd7 : rOne_SMG_Hou <= _7;
4'd8 : rOne_SMG_Hou <= _8;
4'd9 : rOne_SMG_Hou <= _9;
endcase
/***************** Encoder **********************/
/******************** Encoder *******************/
reg [7:0]rData;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
rData <= 8'd0;
else if( Count1 == T4MS )
case( t )
3'd0 : rData <= rOne_SMG_Sec;
3'd1 : rData <= rTen_SMG_Sec;
3'd2 : rData <= rOne_SMG_Min;
3'd3 : rData <= rTen_SMG_Min;
3'd4 : rData <= rOne_SMG_Hou;
3'd5 : rData <= rTen_SMG_Hou;
endcase
/***************************************/
parameter _0 = 8'b1100_0000, _1 = 8'b1111_1001, _2 = 8'b1010_0100,
_3 = 8'b1011_0000, _4 = 8'b1001_1001, _5 = 8'b1001_0010,
_6 = 8'b1000_0010, _7 = 8'b1111_1000, _8 = 8'b1000_0000,
_9 = 8'b1001_0000;
/***************************************/
assign Row_Scan_Sig = rData;
/***************************************/
/* always @(posedge CLK or negedge RSTn ) //????????
begin
if( Counter_Sec == 8'd10) begin spk<= CLK ;end
else if( Counter_Min == 8'd1) spk<= CLK ;
else spk<=0;
end */
endmodule
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