s5pv210 datasheet_system_CONNECTIVITY/ STORAGE

1 UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER
1.1 OVERVIEW OF UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER

The Universal Asynchronous Receiver and Transmitter (UART) in S5PV210 provide four independent

asynchronous, and serial input/output (I/O) ports. All the ports operate in an interrupt-based or a DMA-based
mode. The UART generates an interrupt or a DMA request to transfer data to and from the CPU and the UART.
The UART supports bit rates up to 3Mbps. Each UART channel contains two FIFOs to receive and transmit data:
256 bytes in ch0, 64 bytes in ch1 and 16 bytes in ch2 and ch3.

通用异步接收器和发送器（UART）在S5PV210提供四个独立的

异步串行输入/输出（输入/输出）端口。所有端口工作在在中断或基于DMA的模式。

UART产生中断或DMA请求传输数据从CPU和UART之间。

UART支持比特率高达3Mbps。每个UART通道包含两个FIFO接收和传输数据：

在256字节的通道0，在64字节的CH1，16字节的CH2和CH3。

UART includes programmable baud rates, infrared (IR) transmitter/receiver, one or two stop bit insertion, 5-bit, 6-

bit, 7-bit, or 8-bit data width and parity checking.
Each UART contains a baud-rate generator, a transmitter, a receiver and a control unit, as shown in Figure 1-1.
The baud-rate generator uses PCLK or SCLK_UART. The transmitter and the receiver contain FIFOs and data
shifters. The data to be transmitted is written to Tx FIFO, and copied to the transmit shifter. The data is then
shifted out by the transmit data pin (TxDn). The received data is shifted from the receive data pin (RxDn), and

copied to Rx FIFO from the shifter.

包括可编程UART的波特率，红外（IR）发射机/接收机，一个或两个停止位插入，5位，6—

位，7位，或8位数据宽度和奇偶校验。

每个UART包含波特率发生器，一个发射器，一个接收器和一个控制单元，如图1-1所示。

波特率发生器使用PCLK或sclk_uart。发射器和接收器包含FIFO和数据

移相器。要发送的数据写入TX FIFO，并复制到发送移位器。然后数据

移出的数据传输引脚（txdn）。接收到的数据从接收数据引脚（rxdn），和

复制到RX FIFO的移相器。

1.3.3 AUTO FLOW CONTROL (AFC)
The UART0 and UART1 in S5PV210 support auto flow control (AFC) using nRTS and nCTS signals. UART2
supports auto flow control if TxD3 and RxD3 are set as nRTS2 and nCTS2 by GPA1CON(GPIO SFR). In this
case, it can be connected to external UARTs. To connect UART to a Modem, disable the AFC bit in UMCONn
register and control the signal of nRTS using software.

在S5PV210使用NRTS和nCTS信号支持自动流量控制的UART0和UART1（AFC）。UART2

支持自动流量控制，如果txd3 RXD3是由gpa1con设置为nrts2和ncts2（GPIO SFR）。在这

的情况下，它可以连接到外部UART。连接串口调制解调器，通过umconn寄存器禁用 AFC位

和使用软件控制NRTS信号。

In AFC, the nRTS signal depends on the condition of the receiver, whereas the nCTS signals control the operation
of transmitter. The UART's transmitter transfers the data to FIFO if nCTS signals are activated (in AFC, nCTS
signals means that other UART's FIFO is ready to receive data). Before UART receives data, the nRTS signals
must be activated if its receive FIFO has more than 2-byte as spare. The nRTS signals must be inactivated if its
receive FIFO has less than 1-byte as spare (in AFC, the nRTS signals means that its own receive FIFO is ready to
receive data).

在AFC中，NRTS信号取决于接收机的状态，而nCTS信号控制发射机操作。

UART的传输数据到FIFO，如果nCTS信号激活（AFC，nCTS

信号意味着其他UART的FIFO准备接收数据）。串口接收数据之前，该NRTS信号

必须启动，如果接收FIFO已超过2字节为零。该NRTS信号必须关闭如果

接收FIFO有小于1字节为零（AFC，nRTS信号意味着它拥有的接收FIFO准备去接收数据）。

1.3.7 INTERRUPT/DMA REQUEST GENERATION
Each UART in S5PV210 comprises of seven status (Tx/Rx/Error) signals, namely, Overrun error, Parity error,
Frame error, Break, Receive buffer data ready, Transmit buffer empty, and Transmit shifter empty. These
conditions are indicated by the corresponding UART status register (UTRSTATn/UERSTATn).

在S5PV210每个UART包括七状态（发射/接收/错误）的信号，即溢出错误、奇偶校验错误，

帧错误，中断，接收缓冲数据准备，发送缓冲区空，并发送移位器空。这些

条件是由相应的UART状态寄存器显示（utrstatn / uerstatn）。

The Overrun Error, Parity Error, Frame Error and Break Condition specify the receive error status. If receive-errorstatus-interrupt-enable bit is set to 1 in the control register (UCONn), the receive error status generates receiveerror-status-interrupt. If a receive-error-status-interrupt-request is detected, you can identify the source of interrupt
by reading the value of UERSTATn.

溢出错误，奇偶校验错误，帧错误和中断条件指定接收错误状态。如果收到ErrorStatus中断使能位设置控制寄存器（UConn）为1，接收错误状态产生receiveerror状态中断。如果检测到接收错误状态中断请求，通过阅读uerstatn价值可以识别中断源。

If the receiver transfers data of the receive shifter to the receive FIFO register in FIFO mode, and the number of
received data is greater than or equal to the Rx FIFO Trigger Level, Rx interrupt is generated if Receive mode in
control register (UCONn) is set to 1 (Interrupt request or polling mode).

如果接收机将接收器来接收FIFO数据寄存器在FIFO模式，和一些

接收的数据大于或等于RX FIFO的触发水平，RX中断如果接收模式的产生

控制寄存器（UConn）设置为1（中断请求或轮询方式）。

In Non-FIFO mode, transferring the data of receive shifter to receive holding register causes Rx interrupt in the
Interrupt request and polling modes.

在非FIFO模式，传输数据接收器接收寄存器接收中断的原因持中断请求和轮询模式。

If the transmitter transfers data from its transmit FIFO register to transmit shifter and the number of data left in
transmit FIFO is less than or equal to the Tx FIFO Trigger Level, Tx interrupt is generated (provided Transmit
mode in control register is selected as Interrupt request or polling mode). In Non-FIFO mode, transferring the data
from transmit holding register to transmit shifter causes Tx interrupt in the Interrupt request and polling mode.

如果传输数据从发送FIFO登记发送器和数据放在数

发送FIFO小于或等于Tx FIFO的触发水平，TX中断产生（发送中断设置

控制寄存器的模式选择为中断请求或轮询模式）。在非FIFO模式，传输数据

从发送保持寄存器发送移位导致TX中断的中断请求和轮询模式。

Remember that the Tx interrupt is always requested if the number of data in the transmit FIFO is smaller than the
trigger level. This means that an interrupt is requestedas soon as you enable the Tx interrupt, unless you fill the
Tx buffer. It is recommended to fill the Tx buffer first and then enable the Tx interrupt.

记住，发送中断总是要求如果在发送FIFO数据个数小于触发电平。这意味着，一个中断请求您尽快使TX中断，除非你填充发送缓冲区。

建议填充发送缓冲区并使TX中断。

The interrupt controllers of S5PV210 are of the level-triggered type. You must set the interrupt type as ‘Level’ if
you program the UART control registers.

中断控制器的S5PV210是电平触发式。你必须将中断类型设置为“级别”

如果你编程UART的控制寄存器。

If Receive and Transmit modes in control register are selected as DMAn request mode, then DMAn request
occurs instead of Rx or Tx interrupt in the above situation.

如果接收和发送模式控制寄存器选作为DMA请求模式，然后DMA的请求发生而不是的RX或TX在上述情况下中断。

2IIC-BUS INTERFACE
2.1 OVERVIEW OF IIC-BUS INTERFACE
The S5PV210 RISC microprocessor supports four multi-master I2C bus serial interfaces. To carry information
between bus masters and peripheral devices connected to the I2C bus, adedicated Serial Data Line (SDA) and
an Serial Clock Line (SCL) is used. Both SDA and SCL lines arebi-directional.

S5PV210 RISC微处理器支持四多主I2C总线串行接口。通过I2C总线在主设备和从设备之间进行信息传输，用的是专用的串行数据线（SDA）和

一个串行时钟线（SCL）。SDA和SCL线是双向的。

In multi-master I2C-bus mode, multiple S5PV210 RISC microprocessors receive or transmit serial data to or from
slave devices. The master S5PV210 initiates and terminates a data transfer over the I2C bus. The I2C bus in the
S5PV210 uses a standard bus arbitration procedure.

在多主I2C总线模式，多S5PV210 RISC微处理器接收或发送串行数据或从

从设备。主人S5PV210发起和终止传输通过I2C总线的数据传输。在I2C总线

S5PV210采用标准总线仲裁程序。

To control multi-master I2C-bus operations, values must be written to the following registers:
• Multi-master I2C-bus control register- I2CCON
• Multi-master I2C-bus control/status register- I2CSTAT
• Multi-master I2C-bus Tx/Rx data shift register- I2CDS
• Multi-master I2C-bus address register- I2CADD

控制多主设备I2C总线操作，值必须写入以下寄存器：

•多主设备I2C总线控制寄存器- i2ccon

•多主设备I2C总线控制/状态寄存器- i2cstat

•多主设备I2C总线的TX / RX数据转移寄存器- i2cds

•多主设备I2C总线地址寄存器- i2cadd

If the I2C-bus is free, both SDA and SCL lines should be both at High level. A High-to-Low transition of SDA
initiates a Start condition. A Low-to-High transition of SDA initiates a Stop condition while SCL remains steady at
High Level.

如果I2C总线是空闲的，SDA和SCL线应该在高水平。对低SDA的过渡高

启动条件。低到高的SDA的过渡启动停止条件而SCL仍然稳定在高水平。

The master device always generates Start and Stop conditions. First 7-bit address value in the data byte that is
transferred via SDA line after the Start condition has been initiated, can determine the slave device which the bus
master device has selected. The 8th bit determines the direction of the transfer (read or write).

主设备总是产生启动和停止条件。在开始标志被初始化后开始的头7个位通过SDA线传输的是地址值，可以确定设备的总线

主设备选择。第八位决定了传输的方向（读或写）。

Every data byte put onto the SDA line should be eight bits in total. There is no limit to send or receive bytes during
the bus transfer operation. Data is always sent from most-significant bit (MSB) first, and every byte should be
immediately followed by acknowledge (ACK) bit.

每一个数据字节在SDA线应共八位。在发送或接收字节的过程中没有限制

总线传输操作。数据总是从最显著的位（MSB）开始，每一个字节应

紧随其后的确认（ACK）位。

2.3.1 START AND STOP CONDITIONS
If the I2C-bus interface is inactive, it is usually in Slave mode. In other words, the interface should be in Slave
mode before detecting a Start condition on the SDA line (a Start condition is initiated with a High-to-Low transition
of the SDA line while the clock signal of SCL is High). If the interface state is changed to Master mode, SDA line
initiates data transfer and generates SCL signal.

如果I2C总线接口是无效的，它通常是从模式。换句话说，该接口应该是在从属

检测SDA线开始前的状态模式（启动条件是有高到低过渡的开始

的SDA线，SCL的时钟信号为高）。如果接口状态改变为主模式，SDA线

启动数据传输和产生SCL信号。

A Start condition transfers one-byte serial data via SDA line, and a Stop condition terminates the data transfer. A
Stop condition is a Low-to-High transition of the SDA line while SCL is High. The master generates Start and Stop
conditions. The I2C-bus gets busy if a Start condition is generated. On the other hand, a Stop condition frees the
I2C-bus.

一开始的情况下传输一个字节的串行数据通过SDA线，和一个停止条件终止数据传输。一

停止条件是由低到高的SDA线过渡，当SCL为高。主设备生成开始和停止

条件。如果产生一个起始条件的I2C总线进入忙状态。另一方面，一个停止条件释放

I2C总线。

If a master initiates a Start condition, it should send a slave address to notify the slave device. One byte of
address field consists of a 7-bit address and a 1-bit transfer direction indicator (that shows write or read).
If bit 8 is 0, it indicates a write operation (Transmit Operation); if bit 8 is 1, it indicates a request for data read
(Receive Operation).

如果一个主机启动一个启动条件，它应该发送一个从地址通知从设备。一个字节

地址字段包括7位地址和一位转移方向指示（显示写或读）。

如果位8为0，则表示一个写操作（发送操作）；如果8位为1，则表示一个数据读取的请求

（接收操作）。

The master transmits Stop condition to complete the transfer operation. If the master wants to continue the data
transmission to the bus, it should generate another Start conditionas well as a slave address. In this way, the
read-write operation is performed in various formats.

主设备传输停止条件完成传输操作。如果主要继续数据

传输到总线，它应该产生另一个启动条件，以及作为一个从地址。以这种方式，

在不同的格式进行读写操作。

2.3.2 DATA TRANSFER FORMAT
Every byte placed on the SDA line should be eight bits in length. There is no limit to transmit bytes per transfer.
The first byte following a Start condition should have the address field. If the I2C-bus is operating in Master mode,
master transmits the address field. Each byte should be followed by an acknowledgement (ACK) bit. The MSB bit
of the serial data and addresses are sent first.

每一个字节放在SDA线长度应在八位。传输字节数没有限制。

一个启动条件后的第一个字节应该有地址字段。如果I2C总线主模式操作，

主机传输地址字段。每个字节应紧接在的确认（ACK）位后。MSB位

串行数据和地址被首先发送。

2.3.3 ACK SIGNAL TRANSMISSION
To complete a one-byte transfer operation, the receiver sends an ACK bit to the transmitter. The ACK pulse
occurs at the ninth clock of the SCL line. Eight clocks are required for the one-byte data transfer. The master
generates clock pulse required to transmit the ACK bit.

完成一一个字节的传输操作，接收器发送一个ACK位到发送器。ACK脉冲

发生在SCL时钟线的第九时钟。一个字节的数据传输所需的八个时钟。书设备

产生时钟脉冲需要发送ACK位。

The transmitter sets the SDA line to High to release the SDA line if the ACK clock pulse is received. The receiver
drives the SDA line Low during the ACK clock pulse so that the SDA keeps Low during the High period of the
ninth SCL pulse. The software (I2CSTAT) enables or disables ACK bit transmit function. However, the ACK pulse
on the ninth clock of SCL is required to complete the one-byte data transfer operation.

发射机设置SDA线高，如果收到ACK时钟脉冲释放SDA线。接收机

驱动SDA线低ACK时钟脉冲期间，SDA保持低的时间

第九个时钟脉冲。软件（i2cstat）启用或禁用ACK比特传输功能。然而，ACK脉冲

在SCL第九时钟需要完成一个字节数据传送操作。

3 SERIAL PERIPHERAL INTERFACE
3.1 OVERVIEW OF SERIAL PERIPHERAL INTERFACE
The Serial Peripheral Interface (SPI) in S5PV210 transfers serial data using various peripherals. SPI includes two
8, 16, 32-bit shift registers to transmit and receive data. During an SPI transfer, data issimultaneouslytransmitted
(shifted out serially) and received (shifted in serially). SPI supports the protocols for National Semiconductor
Microwire and Motorola Serial Peripheral Interface.

串行外设接口（SPI）在传输串行数据使用各种S5PV210外设。SPI包括两

16，8，32位移位寄存器来发送和接收数据。一个SPI传输中，数据同时传输

（串行）接收（串行）。SPI支持美国国家半导体的协议

微丝和摩托罗拉串行外设接口。

3.2 KEY FEATURES OF SERIAL PERIPHERAL INTERFACE
The features of SPI include:
• Full duplex
• 8/16/32-bit shift register for TX/RX
• 8-bit Prescaler logic
• 2 clock sources: PCLK and SPI_EXT_CLK from SYSCON
• Supports 8-bit/16-bit/32-bit bus interface
• Supports the Motorola SPI protocol and National Semiconductor Microwire
• Two independent 32-bits wide transmit and receive FIFOs: depth 64 in port 0 and depth 16 in port 1
• Master-mode and Slave-mode
• Receive-without-transmit operation
• Tx/Rx maximum frequency at up to 50MHz

SPI的特点包括：

•全双工

•8 / 16 / 32位为Tx/Rx移位寄存器

•8位预分频器的逻辑

•2个时钟源：来自SYSCON的PCLK和spi_ext_clk

•支持8位/ 16位/ 32位总线接口

•支持摩托罗拉SPI协议和国家半导体微丝

•两个独立的32位的发送和接收FIFO的深度64：在端口1端口0和深度16

•主模式和从属模式

•没有发送操作的接收

•Tx/Rx最大频率可达50MHz

4 USB 2.0 HOST CONTROLLER
4.1 OVERVIEW OF USB 2.0 HOST CONTROLLER
S5PV210 supports a single port USB host interface. The key features of this interface include:
• Complies with Enhanced HCI (EHCI) Rev 1.0a and Open HCI (OHCI) Rev1.0 specifications (Both EHCI and
OHCI compatible).

S5PV210支持单端口USB主机接口。该接口的主要功能包括：

•符合增强人机交互（EHCI）版本1.0A和开放的HCI（OHCI）版本1.0规格（包括投资和

OHCI兼容）。

•Complies with USB Rev 2.0 specification.
• Complies with USB Rev 1.1 specification.
• Supports high-speed (480 Mbps transfer) peripherals.
• Supports power management features, such as:
− Full Suspend/ Resume functionality, including Remote Wakeup
− Over-current protection on ports hooks for master clock suspension

•符合USB 2规范的修订。

•符合USB 1.1规范的修订。

•支持高速（480 Mbps传输）外设。

支持电源管理功能，如：

−全面暂停/恢复功能，包括远程唤醒

在主设备时钟悬浮下端口过载电流保护

5 USB2.0 HS OTG
5.1 OVERVIEW OF USB2.0 HS OTG
Samsung USB On-The-Go (OTG) is a Dual-Role Device (DRD) controller, which supports both device and host
functions. It is fully compliant with the On-The-Go Supplement to the USB 2.0 Specification, Revision 1.0a. It
supports high-speed (HS, 480-Mbps), full-speed (FS, 12-Mbps), and low-speed (LS, 1.5-Mbps, Host only)
transfers. HS OTG can be configured as a Host-only or Device-only controller.

三星USB On-The-Go（OTG）是一种双角色设备（DRD）控制器，它支持设备和主机

功能。这是完全符合在去补充到USB 2规范，修订版1.0a，

支持高速（HS，480 Mbps），全速（FS，12 Mbps），低速（LS，1.5 Mbps，仅主机）

转移。HS OTG可配置为仅主机或设备控制器。

5.2 KEY FEATURES OF USB2.0 HS OTG
The USB2.0 HS OTG features include:
• Complies with the On-The-Go Supplement to the USB 2.0 Specification (Revision 1.0a)
• Operates in High-Speed (480 Mbps), Full-Speed (12 Mbps) and Low-Speed (1.5 Mbps, Host only) modes
• Supports UTMI+ Level 3 interface (Revision 1.0)
• Supports Session Request Protocol (SRP) and Host Negotiation Protocol (HNP)
• Supports only 32-bit data on the AHB
• 1 Control Endpoint 0 for control transfer
• 15 Device Mode programmable Endpoints
− Programmable endpoint type: Bulk, Isochronous, or Interrupt
− Programmable IN/ OUT direction
• Supports 16 Host channels
• Supports packet-based, dynamic FIFO memory allocation of 7936depths (35-bit width)

USB2.0 HS OTG功能包括：

•符合OTG补充到USB 2规范（修订版1.0a）

•工作在高速（480 Mbps），全程高速（12 Mbps）和低速度（1.5 Mbps，仅主机）模式

•支持UTMI + 3级接口（1修订版）

•支持会话请求协议（SRP）和主机协商协议（HNP）

•AHB只支持32位数据

控制传输控制的1个控制端点0

15设备模式可编程端点

−编程端点类型：散装、同步、或中断

−可编程/方向

支持16个主机通道

•支持基于分组的7936depths FIFO（35位宽度）动态内存分配，

6 MODEM INTERFACE
6.1 OVERVIEW OF MODEM INTERFACE
This chapter defines the interface between the Base-band Modem (like MSM) and the Application Processor to
facilitate data-exchange between these two devices. To facilitate data-exchange, S5PV210 include a dual-ported
SRAM buffer (on-chip). To access SRAM buffer, the Modem chip uses a typical asynchronous-SRAM interface.

本章定义的基带调制解调器（如MSM）和应用处理器之间的接口

促进这两者之间的数据交换。为了方便数据交换，S5PV210包括一个双端口

SRAM缓冲区（片）。访问SRAM缓冲器，调制解调器芯片采用典型的异步SRAM的接口。

The size of the SRAM buffer is 16 KB. This specification specifies a few pre-defined special addressees for the
buffer status and interrupts requests.

该SRAM缓冲区的大小是16 KB。本规范为缓存和中断请求规定了一些预定义的地址。

Modem chip writes data in the data buffer (Internal dual port SRAM buffer) and request interrupt to AP. When the
interrupt is asserted, AP reads data in data buffer, and then clears the interrupt. In the samemanner, AP writes
data in the data buffer and then asserts interrupt to modem chip to notify.

调制解调器芯片写入数据到数据缓冲区（内双端口SRAM缓冲器）和请求中断至AP。当

中断是生效，AP在数据缓冲区读取数据，然后清除中断。用同样的方式，

AP在数据缓冲区中写入数据，然后生效中断到调制解调器芯片通知。

7 SD/MMC CONTROLLER
This chapter describes the Secure Digital (SD/ SDIO), MultiMediaCard (MMC), CE-ATA host controller and related
registers supported by S5PV210 RISC microprocessor.
7.1 OVERVIEW OF SD/ MMC CONTROLLER
The SD/ MMC host controller is a combo host for Secure Digital card and MultiMediaCard. This host controller is
based on SD Association’s (SDA) Host Standard Specification.

SD / MMC主机控制器是一个组合的主机安全数字卡和多媒体卡。该主机控制器

基于SD协会（SDA）主机的标准规范。

The SD/ MMC host controller is a interface between system and SD/MMC. The performance of this host is very
powerful, as clock rate is 52-MHz and access 8-bit data pinsimultaneously.

SD / MMC主机控制器系统和SD / MMC接口。这台主机的性能是非常

功能强大，因为时钟速率是52兆赫和访问8位数据引脚同时访问。

7.2 KEY FEATURES OF SD/ MMC CONTROLLER
The High-Speed MMC controller supports:
• SD Standard Host Specification Version 2.0 standard
• SD Memory Card Specification Version 2.0 / High Speed MMC Specification Version 4.3 standard
• SDIO Card Specification Version 1.0 standard
• 512 bytes FIFO for data Tx/ Rx
• CPU Interface and DMA data transfer mode
• 1-bit / 4-bit / 8-bit mode switch
• 8-bit 2 channel, or 4-bit 4 channel
• Auto CMD12
• Suspend/ Resume
• Read Wait operation
• Card Interrupt
• CE-ATA mode

高速MMC控制器支持：

•标准主机规格2标准

•SD记忆卡规范2版/高速MMC规范4.3版标准

•SDIO卡规范1版标准

•512字节FIFO数据发送/接收

•CPU接口和DMA数据传输模式

•1 / 4位或8位模式开关

•8位2通道、4通道或4位

•自动型

暂停/恢复

阅读等待操作

•卡中断

•CE-ATA模式

8 TRANSPORT STREAM INTERFACE
8.1 OVERVIEW OF TRANSPORT STREAM INTERFACE
The Transport Stream Interface (TSI) in S5PV210 receives transport stream data from channel chip, which it
writes to a specific address of the output buffer (SDRAM). Depending on the bus bandwidth, TSI has 32 words
FIFO.

传送流接口（TSI）在接收传输流数据从S5PV210芯片通道，它

写入输出缓冲区的具体地址（SDRAM）。根据不同的总线带宽，TSI 32字的FIFO。

Usingword-aligned address, the TSI sends data streams to the output buffer (SDRAM). One packet size is equal
to 47 words. The output buffer size should be equal to amultiple of 47 words (one packet size).
If the data is written in the output buffer, the SDRAM full interrupt occurs.

使用文字对齐的地址，TSI发送数据流到输出缓冲区（SDRAM）。一个数据包大小是相等的

到47个字。输出缓冲区大小应该是相等的47个字（一个数据包大小）的倍数。

如果数据写入输出缓冲区，SDRAM完全中断发生。

8.1.1 KEY FEATURES OF TRANSPORT STREAM INTERFACE
• Writes transport stream received from channel chip to output buffer (supports 1-/ 4-/ 8-beat burst, wordaligned)
• Supports TS interface in DVB-H/ DVB-T/ ISDB-T/ T-DMB/ DAB mode
• Supports TS_CLK falling/ rising edge data fetch mode
• Supports active high or active low mode for TS signals (TS_VALID, TS_SYNC, and TS_ERROR)
• Supports MSB to LSB or LSB to MSB data byte order
• Specifies the maximum size of output buffer for store transport stream as 256KBytes
• Supports two sync detecting modes:
− TS_SYNC signal
− Sync byte
• Supports PID filter mode with 32 PID filters
• Supports six error cases with SKIP/ STOP mode
• Supports TS_CLK filter.
− TS_CLK maximum frequency
o with TS_CLK filter: ~ 1/2 HCLK
o without TS_CLK filter: ~ 1/4 HCLK

•写传输流从通道芯片输出缓冲器接收（支持1 / 4 / 8拍爆，字对齐）

•支持DVB-H、DVB-T和ISDB-T / T-DMB / DAB模式TS接口

•支持ts_clk下降/上升沿数据读取模式

•支持TS信号高电平或低模式（ts_valid，ts_sync，和ts_error）

•支持MSB到LSB或LSB MSB数据字节顺序

•指定用于存储传输流输出缓冲区的最大大小为256kbytes

支持双同步检测模式：

−ts_sync信号

−同步字节

用32个PID滤波器的PID滤波器模式

·支持六个错误的情况下，跳过/停止模式

•支持ts_clk滤波器。

−ts_clk最大频率

 0，ts_clk过滤器：1 / 2 ~ HCLK

0，没有ts_clk过滤器：1 / 4 ~ HCLK