lpc1788_ucos\uCOSII_cpu\cpu.h --ucosii移植在lpc1788--part2
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/*****************************************************************************************
* uC/CPU
* CPU CONFIGURATION & PORT LAYER
* (c) Copyright 2004-2008; Micrium, Inc.; Weston, FL
* CPU PORT FILE
* ARM-Cortex-M3
* RealView Development Suite
* RealView Microcontroller Development Kit (MDK)
* ARM Developer Suite (ADS)
* Keil uVision
* Filename : cpu.h
* Version : V1.19
* Programmer(s) : JJL
* BAN
******************************************************************************************/
#ifndef CPU_CFG_MODULE_PRESENT
#define CPU_CFG_MODULE_PRESENT
/*****************************************************************************************
* CPU INCLUDE FILES
* Note(s) : (1) The following CPU files are located in the following directories :
* (a) \<CPU-Compiler Directory>\cpu_def.h
* (b) \<CPU-Compiler Directory>\<cpu>\<compiler>\cpu*.*
* where
* <CPU-Compiler Directory> directory path for common CPU-compiler software
* <cpu> directory name for specific CPU
* <compiler> directory name for specific compiler
* (2) Compiler MUST be configured to include the '\<CPU-Compiler Directory>\' directory & the
* specific CPU-compiler directory as additional include path directories.
*****************************************************************************************/
#include "includes.h"
#define DEF_BIT(bit) (1u << (bit))
/*****************************************************************************************
* CONFIGURE STANDARD DATA TYPES
* Note(s) : (1) Configure standard data types according to CPU-/compiler-specifications.
* (2) (a) (1) 'CPU_FNCT_VOID' data type defined to replace the commonly-used function pointer
* data type of a pointer to a function which returns void & has no arguments.
* (2) Example function pointer usage :
* CPU_FNCT_VOID FnctName;
* FnctName();
* (b) (1) 'CPU_FNCT_PTR' data type defined to replace the commonly-used function pointer
* data type of a pointer to a function which returns void & has a single void
* pointer argument.
* (2) Example function pointer usage :
* CPU_FNCT_PTR FnctName;
* void *pobj
* FnctName(pobj);
*****************************************************************************************/
typedef void CPU_VOID;
typedef unsigned char CPU_CHAR; /* 8-bit character */
typedef unsigned char CPU_BOOLEAN; /* 8-bit boolean or logical */
typedef unsigned char CPU_INT08U; /* 8-bit unsigned integer */
typedef signed char CPU_INT08S; /* 8-bit signed integer */
typedef unsigned short CPU_INT16U; /* 16-bit unsigned integer */
typedef signed short CPU_INT16S; /* 16-bit signed integer */
typedef unsigned int CPU_INT32U; /* 32-bit unsigned integer */
typedef signed int CPU_INT32S; /* 32-bit signed integer */
typedef unsigned long long CPU_INT64U; /* 64-bit unsigned integer */
typedef signed long long CPU_INT64S; /* 64-bit signed integer */
typedef float CPU_FP32; /* 32-bit floating point */
typedef double CPU_FP64; /* 64-bit floating point */
typedef void (*CPU_FNCT_VOID)(void); /* See Note #2a. */
typedef void (*CPU_FNCT_PTR )(void *); /* See Note #2b. */
/*****************************************************************************************
* CRITICAL SECTION CONFIGURATION
* Note(s) :
* (1) Configure CPU_CFG_CRITICAL_METHOD with CPU's/compiler's critical section method :
*
* Enter/Exit critical sections by ...
*
* CPU_CRITICAL_METHOD_INT_DIS_EN Disable/Enable interrupts
* CPU_CRITICAL_METHOD_STATUS_STK Push/Pop interrupt status onto stack
* CPU_CRITICAL_METHOD_STATUS_LOCAL Save/Restore interrupt status to local variable
*
* (a) CPU_CRITICAL_METHOD_INT_DIS_EN is NOT a preferred method since it does NOT support
* multiple levels of interrupts. However, with some CPUs/compilers, this is the only
* available method.
*
* (b) CPU_CRITICAL_METHOD_STATUS_STK is one preferred method since it DOES support multiple
* levels of interrupts. However, this method assumes that the compiler allows in-line
* assembly AND will correctly modify the local stack pointer when interrupt status is
* pushed/popped onto the stack.
*
* (c) CPU_CRITICAL_METHOD_STATUS_LOCAL is one preferred method since it DOES support multiple
* levels of interrupts. However, this method assumes that the compiler provides C-level
* &/or assembly-level functionality for the following :
*
* ENTER CRITICAL SECTION :
* (a) Save interrupt status into a local variable
* (b) Disable interrupts
*
* EXIT CRITICAL SECTION :
* (c) Restore interrupt status from a local variable
*
* (2) Critical section macro's most likely require inline assembly. If the compiler does NOT
* allow inline assembly in C source files, critical section macro's MUST call an assembly
* subroutine defined in a 'cpu_a.asm' file located in the following software directory :
*
* \<CPU-Compiler Directory>\<cpu>\<compiler>\
*
* where
* <CPU-Compiler Directory> directory path for common CPU-compiler software
* <cpu> directory name for specific CPU
* <compiler> directory name for specific compiler
*
* (3) To save/restore interrupt status, a local variable 'cpu_sr' of type 'CPU_SR' MAY need to
* be declared (e.g. if 'CPU_CRITICAL_METHOD_STATUS_LOCAL' method is configured). Configure
* 'CPU_SR' data type with the appropriate-sized CPU data type large enough to completely
* store the CPU's/compiler's status word.
******************************************************************************************/
typedef CPU_INT32U CPU_SR; /* Defines CPU status register size (see Note #3). */
/* Configure CPU critical method (see Note #1) : */
#define CPU_CFG_CRITICAL_METHOD CPU_CRITICAL_METHOD_STATUS_LOCAL
#define CPU_CRITICAL_ENTER() { cpu_sr = CPU_SR_Save(); }
#define CPU_CRITICAL_EXIT() { CPU_SR_Restore(cpu_sr); }
/*****************************************************************************************
* CONFIGURE CPU ADDRESS & DATA TYPES
*****************************************************************************************/
/* CPU address type based on address bus size. */
typedef CPU_INT32U CPU_ADDR;
/* CPU data type based on data bus size. */
typedef CPU_INT32U CPU_DATA;
typedef CPU_DATA CPU_ALIGN; /* Defines CPU data-word-alignment size. */
typedef CPU_DATA CPU_SIZE_T; /* Defines CPU standard 'size_t' size. */
/*****************************************************************************************
* FUNCTION PROTOTYPES
*****************************************************************************************/
void CPU_IntDis (void);
void CPU_IntEn (void);
void CPU_IntSrcDis (CPU_INT08U pos);
void CPU_IntSrcEn (CPU_INT08U pos);
CPU_INT16S CPU_IntSrcPrioGet(CPU_INT08U pos);
void CPU_IntSrcPrioSet(CPU_INT08U pos,
CPU_INT08U prio);
CPU_SR CPU_SR_Save (void);
void CPU_SR_Restore (CPU_SR cpu_sr);
CPU_INT32U CPU_CntLeadZeros (CPU_INT32U val);
CPU_INT32U CPU_RevBits (CPU_INT32U val);
void CPU_WaitForInt (void);
void CPU_WaitForExcept(void);
void CPU_BitBandClr (CPU_ADDR addr,CPU_INT08U bit_nbr);
void CPU_BitBandSet (CPU_ADDR addr,CPU_INT08U bit_nbr);
/*****************************************************************************************
* INTERRUPT SERVICES
*****************************************************************************************/
void BSP_IntDisAll (void);
void BSP_IntInit (void);
void BSP_IntEn (CPU_DATA int_id);
void BSP_IntDis (CPU_DATA int_id);
void BSP_IntClr (CPU_DATA int_id);
void BSP_IntVectSet (CPU_DATA int_id, CPU_FNCT_VOID isr);
void BSP_IntPrioSet (CPU_DATA int_id, CPU_INT08U prio);
void WDT_IRQHandler (void);
void TIMER0_IRQHandler (void);
void TIMER1_IRQHandler (void);
void TIMER2_IRQHandler (void);
void TIMER3_IRQHandler (void);
void UART0_IRQHandler (void);
void UART1_IRQHandler (void);
void UART2_IRQHandler (void);
void UART3_IRQHandler (void);
void PWM1_IRQHandler (void);
void I2C0_IRQHandler (void);
void I2C1_IRQHandler (void);
void I2C2_IRQHandler (void);
void SPI_IRQHandler (void);
void SSP0_IRQHandler (void);
void SSP1_IRQHandler (void);
void PLL0_IRQHandler (void);
void RTC_IRQHandler (void);
void EINT0_IRQHandler (void);
void EINT1_IRQHandler (void);
void EINT2_IRQHandler (void);
void EINT3_IRQHandler (void);
void ADC_IRQHandler (void);
void BOD_IRQHandler (void);
void USB_IRQHandler (void);
void CAN_IRQHandler (void);
void DMA_IRQHandler (void);
void I2S_IRQHandler (void);
void ENET_IRQHandler (void);
void RIT_IRQHandler (void);
void MCPWM_IRQHandler (void);
void QEI_IRQHandler (void);
void PLL1_IRQHandler (void);
/******************************************************************************************
* INTERRUPT SOURCES
******************************************************************************************/
#define CPU_INT_STK_PTR 0
#define CPU_INT_RESET 1
#define CPU_INT_NMI 2
#define CPU_INT_HFAULT 3
#define CPU_INT_MEM 4
#define CPU_INT_BUSFAULT 5
#define CPU_INT_USAGEFAULT 6
#define CPU_INT_RSVD_07 7
#define CPU_INT_RSVD_08 8
#define CPU_INT_RSVD_09 9
#define CPU_INT_RSVD_10 10
#define CPU_INT_SVCALL 11
#define CPU_INT_DBGMON 12
#define CPU_INT_RSVD_13 13
#define CPU_INT_PENDSV 14
#define CPU_INT_SYSTICK 15
#define ID_WDT_IRQn 0 /*!< Watchdog Timer Interrupt */
#define ID_TIMER0_IRQn 1 /*!< Timer0 Interrupt */
#define ID_TIMER1_IRQn 2 /*!< Timer1 Interrupt */
#define ID_TIMER2_IRQn 3 /*!< Timer2 Interrupt */
#define ID_TIMER3_IRQn 4 /*!< Timer3 Interrupt */
#define ID_UART0_IRQn 5 /*!< UART0 Interrupt */
#define ID_UART1_IRQn 6 /*!< UART1 Interrupt */
#define ID_UART2_IRQn 7 /*!< UART2 Interrupt */
#define ID_UART3_IRQn 8 /*!< UART3 Interrupt */
#define ID_PWM1_IRQn 9 /*!< PWM1 Interrupt */
#define ID_I2C0_IRQn 10 /*!< I2C0 Interrupt */
#define ID_I2C1_IRQn 11 /*!< I2C1 Interrupt */
#define ID_I2C2_IRQn 12 /*!< I2C2 Interrupt */
#define ID_SPI_IRQn 13 /*!< SPI Interrupt */
#define ID_SSP0_IRQn 14 /*!< SSP0 Interrupt */
#define ID_SSP1_IRQn 15 /*!< SSP1 Interrupt */
#define ID_PLL0_IRQn 16 /*!< PLL0 Lock (Main PLL) Interrupt */
#define ID_RTC_IRQn 17 /*!< Real Time Clock Interrupt */
#define ID_EINT0_IRQn 18 /*!< External Interrupt 0 Interrupt */
#define ID_EINT1_IRQn 19 /*!< External Interrupt 1 Interrupt */
#define ID_EINT2_IRQn 20 /*!< External Interrupt 2 Interrupt */
#define ID_EINT3_IRQn 21 /*!< External Interrupt 3 Interrupt */
#define ID_ADC_IRQn 22 /*!< A/D Converter Interrupt */
#define ID_BOD_IRQn 23 /*!< Brown-Out Detect Interrupt */
#define ID_USB_IRQn 24 /*!< USB Interrupt */
#define ID_CAN_IRQn 25 /*!< CAN Interrupt */
#define ID_DMA_IRQn 26 /*!< General Purpose DMA Interrupt */
#define ID_I2S_IRQn 27 /*!< I2S Interrupt */
#define ID_ENET_IRQn 28 /*!< Ethernet Interrupt */
#define ID_RIT_IRQn 29 /*!< Repetitive Interrupt Timer Interrupt */
#define ID_MCPWM_IRQn 30 /*!< Motor Control PWM Interrupt */
#define ID_QEI_IRQn 31 /*!< Quadrature Encoder Interface Interrupt */
#define ID_PLL1_IRQn 32 /*!< PLL1 Lock (USB PLL) Interrupt */
#define ID_USBActivity_IRQn 33 /*!< USBActivity Interrupt */
#define ID_CANActivity_IRQn 34 /*!< USBActivity Interrupt */
#define ID_UART4_IRQn 35
#define ID_SSP2_IRQn 36
#define ID_LCD_IRQn 37
#define ID_GPIO_IRQn 38
#define ID_PWM0_IRQn 39
#define ID_EEPROM_IRQn 40
/*******************************************************************************************
* CPU REGISTERS
*******************************************************************************************/
#define CPU_REG_NVIC_NVIC (*((volatile CPU_INT32U *)(0xE000E004))) /* Int Ctrl'er Type Reg. */
#define CPU_REG_NVIC_NXP_CTRL (*((volatile CPU_INT32U *)(0xE000E010))) /* SysTick Ctrl & Status Reg. */
#define CPU_REG_NVIC_NXP_RELOAD (*((volatile CPU_INT32U *)(0xE000E014))) /* SysTick Reload Value Reg. */
#define CPU_REG_NVIC_NXP_CURRENT (*((volatile CPU_INT32U *)(0xE000E018))) /* SysTick Current Value Reg. */
#define CPU_REG_NVIC_NXP_CAL (*((volatile CPU_INT32U *)(0xE000E01C))) /* SysTick Calibration Value Reg. */
/* IRQ Set En Reg. */
#define CPU_REG_NVIC_SETEN(n) (*((volatile CPU_INT32U *)(0xE000E100 + (n) * 4)))
/* IRQ Clr En Reg. */
#define CPU_REG_NVIC_CLREN(n) (*((volatile CPU_INT32U *)(0xE000E180 + (n) * 4)))
/* IRQ Set Pending Reg. */
#define CPU_REG_NVIC_SETPEND(n) (*((volatile CPU_INT32U *)(0xE000E200 + (n) * 4)))
/* IRQ Clr Pending Reg. */
#define CPU_REG_NVIC_CLRPEND(n) (*((volatile CPU_INT32U *)(0xE000E280 + (n) * 4)))
/* IRQ Active Reg. */
#define CPU_REG_NVIC_ACTIVE(n) (*((volatile CPU_INT32U *)(0xE000E300 + (n) * 4)))
/* IRQ Prio Reg. */
#define CPU_REG_NVIC_PRIO(n) (*((volatile CPU_INT32U *)(0xE000E400 + (n) * 4)))
#define CPU_REG_NVIC_CPUID (*((volatile CPU_INT32U *)(0xE000ED00))) /* CPUID Base Reg. */
#define CPU_REG_NVIC_ICSR (*((volatile CPU_INT32U *)(0xE000ED04))) /* Int Ctrl State Reg. */
#define CPU_REG_NVIC_VTOR (*((volatile CPU_INT32U *)(0xE000ED08))) /* Vect Tbl Offset Reg. */
#define CPU_REG_NVIC_AIRCR (*((volatile CPU_INT32U *)(0xE000ED0C))) /* App Int/Reset Ctrl Reg. */
#define CPU_REG_NVIC_SCR (*((volatile CPU_INT32U *)(0xE000ED10))) /* System Ctrl Reg. */
#define CPU_REG_NVIC_CCR (*((volatile CPU_INT32U *)(0xE000ED14))) /* Cfg Ctrl Reg. */
#define CPU_REG_NVIC_SHPRI1 (*((volatile CPU_INT32U *)(0xE000ED18))) /* System Handlers 4 to 7 Prio. */
#define CPU_REG_NVIC_SHPRI2 (*((volatile CPU_INT32U *)(0xE000ED1C))) /* System Handlers 8 to 11 Prio. */
#define CPU_REG_NVIC_SHPRI3 (*((volatile CPU_INT32U *)(0xE000ED20))) /* System Handlers 12 to 15 Prio. */
#define CPU_REG_NVIC_SHCSR (*((volatile CPU_INT32U *)(0xE000ED24))) /* System Handler Ctrl & State Reg. */
#define CPU_REG_NVIC_CFSR (*((volatile CPU_INT32U *)(0xE000ED28))) /* Configurable Fault Status Reg. */
#define CPU_REG_NVIC_HFSR (*((volatile CPU_INT32U *)(0xE000ED2C))) /* Hard Fault Status Reg. */
#define CPU_REG_NVIC_DFSR (*((volatile CPU_INT32U *)(0xE000ED30))) /* Debug Fault Status Reg. */
#define CPU_REG_NVIC_MMFAR (*((volatile CPU_INT32U *)(0xE000ED34))) /* Mem Manage Addr Reg. */
#define CPU_REG_NVIC_BFAR (*((volatile CPU_INT32U *)(0xE000ED38))) /* Bus Fault Addr Reg. */
#define CPU_REG_NVIC_AFSR (*((volatile CPU_INT32U *)(0xE000ED3C))) /* Aux Fault Status Reg. */
#define CPU_REG_NVIC_PFR0 (*((volatile CPU_INT32U *)(0xE000ED40))) /* Processor Feature Reg 0. */
#define CPU_REG_NVIC_PFR1 (*((volatile CPU_INT32U *)(0xE000ED44))) /* Processor Feature Reg 1. */
#define CPU_REG_NVIC_DFR0 (*((volatile CPU_INT32U *)(0xE000ED48))) /* Debug Feature Reg 0. */
#define CPU_REG_NVIC_AFR0 (*((volatile CPU_INT32U *)(0xE000ED4C))) /* Aux Feature Reg 0. */
#define CPU_REG_NVIC_MMFR0 (*((volatile CPU_INT32U *)(0xE000ED50))) /* Memory Model Feature Reg 0. */
#define CPU_REG_NVIC_MMFR1 (*((volatile CPU_INT32U *)(0xE000ED54))) /* Memory Model Feature Reg 1. */
#define CPU_REG_NVIC_MMFR2 (*((volatile CPU_INT32U *)(0xE000ED58))) /* Memory Model Feature Reg 2. */
#define CPU_REG_NVIC_MMFR3 (*((volatile CPU_INT32U *)(0xE000ED5C))) /* Memory Model Feature Reg 3. */
#define CPU_REG_NVIC_ISAFR0 (*((volatile CPU_INT32U *)(0xE000ED60))) /* ISA Feature Reg 0. */
#define CPU_REG_NVIC_ISAFR1 (*((volatile CPU_INT32U *)(0xE000ED64))) /* ISA Feature Reg 1. */
#define CPU_REG_NVIC_ISAFR2 (*((volatile CPU_INT32U *)(0xE000ED68))) /* ISA Feature Reg 2. */
#define CPU_REG_NVIC_ISAFR3 (*((volatile CPU_INT32U *)(0xE000ED6C))) /* ISA Feature Reg 3. */
#define CPU_REG_NVIC_ISAFR4 (*((volatile CPU_INT32U *)(0xE000ED70))) /* ISA Feature Reg 4. */
#define CPU_REG_NVIC_SW_TRIG (*((volatile CPU_INT32U *)(0xE000EF00))) /* Software Trigger Int Reg. */
#define CPU_REG_MPU_TYPE (*((volatile CPU_INT32U *)(0xE000ED90))) /* MPU Type Reg. */
#define CPU_REG_MPU_CTRL (*((volatile CPU_INT32U *)(0xE000ED94))) /* MPU Ctrl Reg. */
#define CPU_REG_MPU_REG_NBR (*((volatile CPU_INT32U *)(0xE000ED98))) /* MPU Region Nbr Reg. */
#define CPU_REG_MPU_REG_BASE (*((volatile CPU_INT32U *)(0xE000ED9C))) /* MPU Region Base Addr Reg. */
#define CPU_REG_MPU_REG_ATTR (*((volatile CPU_INT32U *)(0xE000EDA0))) /* MPU Region Attrib & Size Reg. */
#define CPU_REG_DBG_CTRL (*((volatile CPU_INT32U *)(0xE000EDF0))) /* Debug Halting Ctrl & Status Reg. */
#define CPU_REG_DBG_SELECT (*((volatile CPU_INT32U *)(0xE000EDF4))) /* Debug Core Reg Selector Reg. */
#define CPU_REG_DBG_DATA (*((volatile CPU_INT32U *)(0xE000EDF8))) /* Debug Core Reg Data Reg. */
#define CPU_REG_DBG_INT (*((volatile CPU_INT32U *)(0xE000EDFC))) /* Debug Except & Monitor Ctrl Reg. */
#define CPU_REG_NVIC_SHCSR_USGFAULTENA 0x00040000
#define CPU_REG_NVIC_SHCSR_BUSFAULTENA 0x00020000
#define CPU_REG_NVIC_SHCSR_MEMFAULTENA 0x00010000
#define CPU_REG_NVIC_SHCSR_SVCALLPENDED 0x8000
#define CPU_REG_NVIC_SHCSR_BUSFAULTPENDED 0x4000
#define CPU_REG_NVIC_SHCSR_MEMFAULTPENDED 0x2000
#define CPU_REG_NVIC_SHCSR_USGFAULTPENDED 0x1000
#define CPU_REG_NVIC_SHCSR_SYSTICKACT 0x0800
#define CPU_REG_NVIC_SHCSR_PENDSVACT 0x0400
#define CPU_REG_NVIC_SHCSR_MONITORACT 0x0100
#define CPU_REG_NVIC_SHCSR_SVCALLACT 0x80
#define CPU_REG_NVIC_SHCSR_USGFAULTACT 0x08
#define CPU_REG_NVIC_SHCSR_BUSFAULTACT 0x02
#define CPU_REG_NVIC_SHCSR_MEMFAULTACT 0x01
/* ---------- SYSTICK CTRL & STATUS REG BITS ---------- */
#define CPU_REG_NVIC_NXP_CTRL_COUNTFLAG 0x00010000
#define CPU_REG_NVIC_NXP_CTRL_CLKSOURCE 0x04
#define CPU_REG_NVIC_NXP_CTRL_TICKINT 0x02
#define CPU_REG_NVIC_NXP_CTRL_ENABLE 0x01
/* -------- SYSTICK CALIBRATION VALUE REG BITS -------- */
#define CPU_REG_NVIC_NXP_CAL_NOREF 0x80000000
#define CPU_REG_NVIC_NXP_CAL_SKEW 0x40000000
#define DEF_OCTET_NBR_BITS 8
#define DEF_OCTET_MASK 0xFF
#define DEF_INT_16S_MIN_VAL -32768
#define DEF_INT_16S_MAX_VAL 32767
/*****************************************************************************************
* MODULE END
*****************************************************************************************/
#endif
- lpc1788_ucos\uCOSII_cpu\cpu.h --ucosii移植在lpc1788--part2
- lpc1788_ucos\uCOSII_cpu\os_cpu_c.c --ucosii移植在lpc1788--part5
- lpc1788_ucos\uCOSII_cpu\os_cpu.h cpu_c.c --ucosii移植在lpc1788--part4-part1
- lpc1788_ucos\uCOSII_cpu\os_cpu.h cpu_c.c --ucosii移植在lpc1788--part4-part12
- lpc1788_ucos\uCOSII_cpu\cpu_a.asm os_cpu_a.asm --ucosii移植在lpc1788--part3
- lpc1788_ucos\cmsis\include.h bsp.h.c --ucosii移植在lpc1788--part7
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