UVM overwrite

    `ifndef TEST_COLLECTION__SV    `define TEST_COLLECTION__SV    `include "router_env.sv"    class test_base extends uvm_test;      `uvm_component_utils(test_base)  router_env env;  function new(string name, uvm_component parent);    super.new(name, parent);    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);  endfunction  virtual function void build_phase(uvm_phase phase);    super.build_phase(phase);    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);    env = router_env::type_id::create("env", this);  endfunction//// The start_of_simulation_phase method from lab1 is moved to final_phase// for the convinience of seeing the topology and factory registry at the// end of simulation.  In practice, you should implement both phases to// display the topology and the factory registry.//  virtual function void final_phase(uvm_phase phase);    super.final_phase(phase);    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);    uvm_top.print_topology();    factory.print();  endfunctionendclass// Lab 2 - Include the packet_da_3.sv file//// ToDoinclude packet_da_3.svclass test_da_3_inst extends test_base;  `uvm_component_utils(test_da_3_inst)  function new(string name, uvm_component parent);    super.new(name, parent);    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);  endfunction  virtual function void build_phase(uvm_phase phase);    super.build_phase(phase);    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);    // Lab 2 - Use instance override to configure the packet sequencer    //         to use packet_da_3 instead of packet    //    // ToDo

set_inst_override_by_type("env.i_agent*.seqr.*",packet::get_type(),pacet_da_3::get_type());

//这是覆盖原来的约束的方法 override_by_type()  endfunctionendclass// Optional Lab 2 - Create a test to globally set all packet instances to packet_da_3`endif

//覆盖之后要使用的就是新的UVM test了，所以仿真的时候，大概是test_top都变了呢
Compile and simulate the testbench

make test=test_da_3_inst// 编译指令，大概是对make file里文件的改写方法

——————————分割线———————————
// The start_of_simulation_phase method from lab1 is moved to final_phase
// for the convinience of seeing the topology and factory registry at the
// end of simulation. In practice, you should implement both phases to
// display the topology and the factory registry.

      virtual function void final_phase(uvm_phase phase);        super.final_phase(phase);        `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);        uvm_top.print_topology();        factory.print();      endfunction    endclass

用 uvm_top.print_topology();打印UVM树，

UVM_INFO @ 0.0ns: reporter [UVMTOP] UVM testbench topology:--------------------------------------------------------------Name                       Type                    Size  Value--------------------------------------------------------------uvm_test_top               test_base               -     @455  env                      router_env              -     @463    i_agent                input_agent             -     @471      drv                  driver                  -     @610        rsp_port           uvm_analysis_port       -     @627        seq_item_port      uvm_seq_item_pull_port  -     @618      seqr                 uvm_sequencer           -     @487        rsp_export         uvm_analysis_export     -     @495        seq_item_export    uvm_seq_item_pull_imp   -     @601        arbitration_queue  array                   0     -        lock_queue         array                   0     -        num_last_reqs      integral                32    'd1        num_last_rsps      integral                32    'd1--------------------------------------------------------------

用 factory.print();打印注册的文件，以及覆盖关系

#### Factory Configuration (*)Instance Overrides:  Requested Type  Override Path                     Override Type  --------------  --------------------------------  -------------  packet          uvm_test_top.env.i_agent*.seqr.*  packet_da_3No type overrides are registered with this factoryAll types registered with the factory: 45 total(types without type names will not be printed)  Type Name  ---------  driver  input_agent  packet  packet_da_3  packet_sequence  router_env  snps_uvm_reg_bank_group  snps_uvm_reg_map  test_base  test_da_3_inst(*) Types with no associated type name will be printed as <unknown>####